參數(shù)資料
型號(hào)： CLC5902VLA
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 調(diào)諧器
英文描述： Dual Digital Tuner/AGC
中文描述： 1-BAND, AUDIO TUNER, PQFP128
封裝： PLASTIC, QFP-128
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 783K
代理商： CLC5902VLA
Rev. 3.05 May 27, 1999
18
1999 National Semiconductor Corporation
Output Modes
After processing by the DDC, the data is then formatted
for output.
Note
All output data is two’s complement.
Output formats include truncation to 8 or 32 bits, rounding
to 16 or 24 bits, and a 12-bit floating point format (4-bit
exponent, 8-bit mantissa, 138dB numeric range). This
function is performed in the OUTPUT CIRCUIT shown in
Figure 28.
The channel outputs are accessible through serial output
pins and a 16-bit parallel output port. The
RDY
pin is pro-
vided to notify the user that a new output sample period
(OSP) has begun. OSP refers to the interval between out-
put samples at the decimated output rate. For example, if
the input rate (and clock rate) is 52 MHz and the overall
decimation factor is 192 (N=48, F2 decimation=2) the
OSP will be 3.69 microseconds which corresponds to an
output sample rate of 270.83kHz. An OSP starts when a
sample is ready and stops when the next one is ready.
Note
The serial outputs power up in a tri-state
condition and must be enabled when the chip
is configured. Parallel outputs are enabled by
the POUT_EN pin.
Serial Outputs
The CLC5902 provides a serial clock (
SCK
), a frame
strobe (
SFS
) and two data lines (
AOUT
and
BOUT
) to
output serial data. The MUX_MODE control register
specifies whether the two channel outputs are transmitted
on two separate serial pins, or multiplexed onto one pin in
a time division multiplexed (TDM) format. Separate out-
put pins are not provided for the I and Q halves of com-
plex data. The I and Q outputs are always multiplexed
onto the same serial pin. The I-component is output first,
followed by the Q-component. By setting the PACKED
mode bit to ‘1’ a complex pair may be treated as a single
double-wide word. The
RDY
signal is used to identify the
first word of a complex pair of the TDM formatted output.
The TDM modes are summarized in Table 2.
The serial outputs use the format shown in Figure 29. Fig-
ure 29(a) shows the standard output mode (the PACKED
mode bit is low). The chip clocks the frame and data out of
the chip on the rising edge of
SCK
(or falling edge if the
SCK_POL bit in the input control register is set high).
Data should be captured on the falling edge of
SCK
(ris-
ing if SCK_POL=1). The chip sends the I data first by set-
ting
SFS
high (or low if SFS_POL in the input control
register is set high) for one clock cycle, and then transmit-
ting the data, MSB first, on as many
SCK
cycles as are
necessary. Without a pause, the Q data is transferred next
as shown in Figure 29(a). If the PACKED control bit is
high, then the I and Q components are sent as a double
length word with only one
SFS
strobe as shown in Figure
29(b). If both channels are multiplexed out the same serial
pin, then the subsequent I/Q channel words will be trans-
mitted immediately following the first I/Q pair as shown
in Figure 29(c). Figure 29(c) also shows how the
RDY
signal can be used to identify the I and Q channels in the
TDM serial transmission.The serial output rate is pro-
grammable using the RATE register as a integer division
of the input clock, the division ratio ranging from 1 to 256.
The serial interface will not work properly if the pro-
grammed rate of
SCK
is insufficient to clock out all the
bits in one OSP.
Serial Port Output Number Formats
Several numeric formats are selectable using the FOR-
MAT control register. The I/Q samples can be rounded to
16 or 24 bits, or truncated to 8 bits. The packed mode
works as described above for these fixed point formats. A
floating point format with 138dB of dynamic range in 12
bits is also provided. The mantissa (m) is 8 bits and the
exponent (e) is 4 bits. The MSB of each segment is trans-
DIVIDE
BY
RATE
BOUT
AOUT
16
POUT_SEL[2..0]
POUT[15..0]
C
C
S
POUT_EN
CK
SCK
3
RDY
MUX
N
C
F
T
P
M
P
RDY_POL, SCK_POL, SFS_POL
Figure 28
CLC5902 output circuit
SFS
MUX_MODE
SERIAL OUTPUTS
AOUT
BOUT
0
OUT
A
OUT
B
1
OUT
A
, OUT
B
LOW
Table 2
TDM Modes
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參數(shù)描述
CLC5903 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC
CLC5903CISM/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903SM 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903SM/NOPB 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
CLC5903VLA 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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