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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 783K |
| 代理商： | CLC5902VLA |
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1999 National Semiconductor Corporation
15
Rev. 3.05 May 27, 1999
The CIC filter has a gain equal to N
4
(filter decimation^4)
which must be compensated for in the “SHIFT UP” circuit
shown in Figure 19 as well as Figure 15. This circuit has a
gain equal to 2
(SCALE-44)
, where SCALE ranges from 0 to
40. This circuit divides the input signal by 2
44
providing
maximum headroom through the CIC filter. For optimal
noise performance the SCALE value is set to increase this
level until the CIC filter is just below the point of distor-
tion. A value is normally calculated and loaded for
SCALE such that
actual gain of the CIC filter will only be unity for power-
of-two decimation values. In other cases the gain will be
somewhat less than unity.
. The
Channel Gain
The gain of each channel can be boosted up to 42 dB by
shifting the output of the CIC filter up by 0 to 7 bits prior
to rounding it to 21 bits. For channel A, the gain of this
stage is:
, where GAIN_A ranges from 0
to 7. Overflow due to the GAIN circuit is saturated
(clipped) at plus or minus full scale. Each channel can be
given its own GAIN setting.
First Programmable FIR Filter (F1)
The CIC/GAIN outputs are followed by two stages of fil-
tering. The first stage is a 21 tap decimate-by-2 symmetric
FIR filter with programmable coefficients. Typically, this
filter compensates for a slight droop induced by the CIC
filter. In addition, it often provides stopband assistance to
F2 when deep stop bands are required. The filter coeffi-
cients are 16-bit 2’s complement numbers. Unity gain will
be achieved through the filter if the sum of the 21 coeffi-
cients is equal to 2
16
. If the sum is not 2
16
, then F1 will
introduce a gain equal to (sum of coefficients)/2
16
. The 21
coefficients are identified as coefficients
where
The coefficients are symmetric, so only the first 11 are
loaded into the chip.
is the center tap.
Two example sets of coefficients are provided here. The
first set of coefficients, referred to as the standard set
(STD), compensates for the droop of the CIC filter provid-
ing a passband which is flat (0.01 dB ripple) over 95% of
the final output bandwidth with 70dB of out-of-band rejec-
tion (see Figure 20). The filter has a gain of 0.999 and is
symmetric with the following 11 unique taps (1|21, 2|20,
..., 10|12, 11):
29, -85, -308, -56, 1068, 1405, -2056, -6009,
1303, 21121, 32703
The second set of coefficients (GSM set) are intended for
applications that need deeper stop bands or need oversam-
pled outputs. These requirements are common in cellular
systems where out of band rejection requirements can
exceed 100dB (see Figure 21). They are useful for wide-
band radio architectures where the channelization is done
after the ADC. These filter coefficients introduce a gain of
0.984 and are:
-49, -340, -1008, -1617, -1269, 425, 3027, 6030,
9115, 11620, 12606
Second Programmable FIR Filter (F2)
The second stage decimate by two or four filter also uses
externally downloaded filter coefficients. The filter coeffi-
cients are 16-bit 2’s complement numbers. Unity gain will
be achieved through the filter if the sum of the 63 coeffi-
cients is equal to 2
16
. If the sum is not 2
16
, then the F2 will
introduce a gain equal to (sum of coefficients)/2
16
.
The 63 coefficients are identified as
where
is the center tap. The coefficients are sym-
metric, so only the first 32 are loaded into the chip.
DIN
OUT
D
B
O
SCALE
S
22
Figure 19
Four-stage decimate by N CIC filter
66
Data @ F
CK
= F
S
(F
SAMPLE
)
Data @ F
CK
/N
N = DEC + 1
22-bit input to SHIFT_UP is aligned
at the bottom of the 66-bit path when SCALE=0.
GAIN
SHIFTUP
GAIN
CIC
1
≤
GAIN
2
GAIN_A
=
h
1
n
( )
n
,
0
…
20
,
,
=
h
1
10
(
)
Figure 20
F1 STD frequency response
0
0.1
0.2
0.3
0.4
0.5
100
90
80
70
60
50
40
30
20
10
0
Frequency Response of F1 Using STD Set
M
Frequency Normalized To Filter Input Sample Rate
h
2
n
( )
n
0
…
62
,
,
=
,
h
2
31
(
)
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| CLC5903 | Dual Digital Tuner / AGC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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