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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大小： | 783K |
| 代理商： | CLC5902VLA |
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1999 National Semiconductor Corporation
25
Rev. 3.05 May 27, 1999
scale) to detected power levels (54 db range). This pro-
vides a resolution of 1.7dB between detected power levels.
The truth table for this converter is given in Table 6. The
upper three bits of the output represent the exponent (e)
and the lower 2 are the mantissa (m). The exponent is
determined by the position of the leading ‘1’ out of the
CIC filter. An output of ‘001XX’ corresponds to a leading
‘1’ in bit 2 (LSB is bit 0). The exponent increases by one
each time the leading ‘1’ advances in bit position. The
mantissa bits are the two bits that follow the leading ‘1’. If
we define E as the decimal value of the exponent bits and
M as the decimal value of the mantissa bits, the output of
the CIC filter, P
OUT
, corresponding to a given “FIXED TO
FLOAT CONVERTER” output is,
EQ. 5
The max() and min() operators account for row 1 of Table
6 which is a special case because M=P
OUT
. Equation 5
associates each address of the RAM with a CIC filter out-
put.
As shown in Figure 32, the 32X8 RAM look-up table
implements the functions of log converter, reference sub-
traction, error amplifier, and deadband. The user must
build each of these functions by constructing a set of 8-bit,
2’s complement numbers to be loaded into the RAM. Each
of these functions and how to construct them are discussed
in the following paragraphs.
A log conversion is done in order to keep the loop gain
independent of operating point. To see why this is benefi-
cial, the control gain of the DVGA computed without log
conversion is,
EQ. 6
where G is the decimal equivalent of GAIN and G
o
accounts for the DVGA gain in excess of unity. This equa-
tion assumes that the DVGA gain control polarity is posi-
tive as is the case for the CLC5526. The gain around the
entire loop must be negative. Observe in Equation 6 that
the control gain is dependent on operating point G. If we
instead compute the control gain with log conversion,
EQ. 7
which is no longer operating-point dependent. The log
function is constructed by computing the CIC filter output
associated with each address (Equation 5) and converting
these to dB. Full scale (dc signal) is
.
The reference subtraction is constructed by subtracting the
desired loop servo point (in dB) from the table values
computed in the previous paragraph. For example, if it is
desired that the DVGA servo the ADC input level (sinuso-
idal signal) to -6dBFS, the number to subtract from the
data is
.
EQ. 8
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider
than 6dB should then be constructed symmetrically about
this point. This prevents the loop from hunting due to the
6dB gain steps of the DVGA. Any deadband in excess of
6dB appears as hysteresis in the servo point of the loop as
illustrated in Figure 31. The deadband is constructed by
loading zeros into those addresses on either side of the one
which corresponds to the reference level.
The last function of the RAM table is that of error amplifi-
cation. All the operations preceding this one gave a table
slope
. This must now be adjusted in order to
control the time constant of the loop given by,
INPUT
OUTPUT
(eeemm)
0-3
000XX
4-7
001XX
8-15
010XX
16-31
011XX
32-63
100XX
64-127
101XX
128-255
110XX
256-511
111XX
Table 6
Fixed to Float Converter Truth Table
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-60
-50
-40
-30
-20
-10
0
Frequency Normalized to Sample Rate
M
Figure 34
Power detector filter response
P
OUT
4
min E
1
2
max E
1
,
,
)
)
E
,
M
+
[
]
)
1
–
(
1.
≥
=
K
DVGA
′
G
v
i
2
G
G
o
–
(
)
(
)
,
=
v
i
2
( )
2
G
G
o
–
(
)
,
ln
–
=
K
DVGA
G
6.02,
–
20
v
i
2
G
G
o
–
(
)
(
)
log
[
]
,
=
=
20
511
(
)
54
dB
=
log
20
2
511
2
π
--
44
dB
=
log
S
RAM
1
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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