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參數(shù)資料
| 型號： | CLC5902VLA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | Dual Digital Tuner/AGC |
| 中文描述： | 1-BAND, AUDIO TUNER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 783K |
| 代理商： | CLC5902VLA |
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1999 National Semiconductor Corporation
13
Rev. 3.05 May 27, 1999
The “FLOAT TO FIXED CONVERTER” circuit expands
the dynamic range compression performed by the DVGA.
Signals from this point onward extend across the full
dynamic range of the signals applied to the DVGA input.
This allows the AGC to operate continuously through a
burst without producing artifacts in the signal due to the
settling response of the decimation filters after a 6dB
DVGA gain adjustment. For example, if the DVGA input
signal were to increase causing the ADC output level to
cross the AGC threshold level, the gain of the DVGA
would change by -6dB. The 6dB step is allowed to propa-
gate through the ADC and mixers and is compensated out
just before the filtering. The accuracy of the compensation
is dependent on the accuracy of the DVGA gain step. This
operating mode requires 21 bits (14-bit ADC output + 7-
bit shift) to represent the full linear dynamic range of the
signal. The output word must be set to either 24-bit or 32-
bit to take advantage of the entire dynamic range avail-
able. The CLC5902 can also be configured to output a
floating point format with up to 138dB of numerical reso-
lution using only 12 output bits.
The “SHIFT UP” circuit will be discussed in the Four
Stage CIC filter section on page 14.
A 4-stage cascaded-integrator-comb (CIC) filter and a
two-stage decimate by 4 or 8 finite impulse response (FIR)
filter are used to lowpass filter and isolate the desired sig-
nal. The CIC filter reduces the sample rate by a program-
mable factor ranging from 8 to 2048 (decimation ratio).
The CIC outputs are followed by a gain stage and then fol-
lowed by a two-stage decimate by 4 or 8 filter. The gain
circuit allows the user to boost the gain of weak signals by
up to 42 dB in 6 dB steps. It also rounds the signal to 21
bits and saturates at plus or minus full scale.
The first stage of the two stage filter is a 21-tap, symmetric
decimate by 2 FIR filter (F1) with programmable 16 bit
tap weights. The coefficients of the first 11 taps are down-
loaded to the chip as 16 bit words. Since the filter is a sym-
metric configuration only the first 11 coefficients must be
loaded. The F1 section on page 15 provides a generic set
of coefficients that compensate for the rolloff of the CIC
filter and provide a passband flat to 0.01dB with 70 dB of
out of band rejection. A second coefficient set is provided
that has a narrower output passband and greater out-of-
band rejection. The second set of coefficients is ideal for
systems such as GSM where far-image rejection is more
important than adjacent channel rejection.
The second stage is a 63 tap decimate by 2 or 4 program-
mable FIR filter (F2) also with 16 bit tap weights. Filter
coefficients for a flat response from -0.4F
S
to +0.4F
S
of
the output sample rate with 80dB of out of band rejection
are provided in the F2 section. A second set of F2 coeffi-
cients is also provided to enhance performance for GSM
systems. The user can also design and download their own
final filter to customize the channel’s spectral response.
Typical uses of programmable filter F2 include matched
(root-raised cosine) filtering, or filtering to generate over-
sampled outputs with greater out of band rejection. The 63
tap symmetrical filter is downloaded into the chip as 32
words, 16 bits each. Saturation to plus or minus full scale
is performed at the output of F1 and F2 to clip the signal
rather than allow it to roll over.
The Numerically Controlled Oscillator
The tuning frequency of each down converter is specified
as a 32 bit word (.02Hz resolution at
CK
=52MHz) and the
phase offset is specified as a 16 bit word (.005°). These
two parameters are applied to the Numerically Controlled
(a) Before Phase Dithering
(b) After Phase Dithering
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency Normalized to F
S
Frequency Normalized to F
S
M
M
Figure 16
Example of NCO spurs due to phase truncation
Complex NCO Output
Complex NCO Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CLC5903 | Dual Digital Tuner / AGC |
| CLC5903SM | Dual Digital Tuner / AGC |
| CLC5903VLA | Dual Digital Tuner / AGC |
| CLC5955 | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
| CLC5955MTDX | 11-bit, 55MSPS Broadband Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLC5903 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual Digital Tuner / AGC |
| CLC5903CISM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903SM/NOPB | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| CLC5903VLA | 功能描述:上下轉(zhuǎn)換器 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
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