參數(shù)資料
型號(hào)： BX80562X3210SLACU
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775
封裝： LGA-775
文件頁(yè)數(shù)： 68/96頁(yè)
文件大?。?/td> 1398K
代理商： BX80562X3210SLACU
Land Listing and Signal Descriptions
70
Quad-Core Intel Xeon Processor 3200 Series Datasheet
RESET#
Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least one millisecond after
VCC and BCLK have reached their proper specifications. On observing active
RESET#, all FSB agents will de-assert their outputs within two clocks. RESET#
must not be kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are
described in the Section 6.1.
This signal does not have on-die termination and must be terminated on the
system board.
RESERVED
All RESERVED lands must remain unconnected. Connection of these lands to
VCC, VSS, VTT, or to any other signal (including each other) can result in
component malfunction or incompatibility with future processors.
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins/lands of all processor FSB agents.
SKTOCC#
Output
SKTOCC# (Socket Occupied) will be pulled to ground by the processor.
System board designers may use this signal to determine if the processor is
present.
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-
state its outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core
units except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK#
is de-asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI, TDI_M
Input
TDI and TDI_M (Test Data In) transfer serial test data into the processor
cores. TDI and TDI_M provide the serial input needed for JTAG specification
support. TDI connects to core 0. TDI_M connects to core 1.
TDO, TDO_M
Output
TDO and TDO_M (Test Data Out) transfer serial test data out of the processor
cores. TDO and TDI_M provide the serial output needed for JTAG specification
support. TDO connects to core 1. TDO_M connects to core 0.
TESTHI[13,
11:10,7:0]
Input
TESTHI[13,11:10,7:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
description) through a resistor for proper processor operation. See
Section 2.4 for more details.
THERMTRIP#
Output
In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum T
C. Assertion of THERMTRIP# (Thermal Trip) indicates
the processor junction temperature has reached a level beyond where
permanent silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect the
processor, its core voltage (V
CC) must be removed following the assertion of
THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of
the assertion of PWRGOOD (provided VTT and VCC are valid) and is disabled
on de-assertion of PWRGOOD (if VTT or VCC are not valid, THERMTRIP# may
also be disabled). Once activated, THERMTRIP# remains latched until
PWRGOOD, VTT, or VCC is de-asserted. While the de-assertion of the
PWRGOOD, VTT, or VCC will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will again be
asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are
valid).
Table 4-3.
Signal Description (Sheet 5 of 6)
Name
Type
Description
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