- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223478 > BX80562X3210SLACU (INTEL CORP) 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 PDF資料下載
參數(shù)資料
| 型號： | BX80562X3210SLACU |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 66/96頁 |
| 文件大?。?/td> | 1398K |
| 代理商： | BX80562X3210SLACU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當(dāng)前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
Quad-Core Intel Xeon Processor 3200 Series Datasheet
69
Land Listing and Signal Descriptions
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions.
If IGNNE# is de-asserted, the processor generates an exception on a
noncontrol floating-point instruction if a previous floating-point instruction
caused an error. IGNNE# has no effect when the NE bit in control register 0
(CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an Input/Output write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus
transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers inside the
processor without affecting its internal caches or floating-point registers. The
processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins/lands of all processor FSB agents.
ITP_CLK[1:0]
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an interposer.
If a debug port is implemented in the system, ITP_CLK[1:0] are no connects
in the system. These are not processor signals.
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/lands of
all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes
INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are
asynchronous.
Both of these signals must be software configured via BIOS programming of
the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these signals as
LINT[1:0] is the default configuration.
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins/lands of all processor FSB agents.
For a locked sequence of transactions, LOCK# is asserted from the beginning
of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# de-asserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
PECI
Input/
Output
PECI is a proprietary one-wire bus interface. See Section 5.3 for details.
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit (TCC) has been activated, if enabled. As an input,
assertion of PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#. See
Section 5.2.4 for more details.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable
and within their specifications. ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/lands of
all processor FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB0#.
Table 4-3.
Signal Description (Sheet 4 of 6)
Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX80616I5660SLBLV | 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156 |
| BXA10-48D15-S | DC to DC Converter |
| BXA10-48S05 | EMI FILTER INCLUDING ESD PROTECTION |
| BXA10-48S05-S | 8 line low capacitance EMI filter and ESD protection |
| BXA10-48S12 | 9-line IPAD", EMI filter and ESD protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80563E5310A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel???? Xeon???? Processor E5310 |
| BX80563E5310ASL9XR | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel???? Xeon???? Processor E5310 |
| BX80563E5310P | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel???? Xeon???? Processor E5310 |
| BX80563X5355A S LAC4 | 制造商:Intel 功能描述:32BIT MPU BX80563X5355A 2.66G |
| BX80563X5355P S LAC4 | 制造商:Intel 功能描述:32BIT MPU BX80563X5355P 2.66G |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。