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參數(shù)資料
| 型號： | BR1570 |
| 英文描述： | WarpLink Reference Design Platform |
| 中文描述： | WarpLink參考設計平臺 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 492K |
| 代理商： | BR1570 |
WarpLink Reference Design Platform
7
For More Information On This Product,
Go to: www.freescale.com
Backplane/Chassis Design Considerations
Before we discuss the details of the Motorola WarpLink backplane, it would be helpful to give an overview of the process and constraints
under which a backplane and chassis are designed. The design of the backplane must consider the design elements of the system as a
whole. The major parameters that shape a chassis/backplane system must be established early on in the design, once the intended market
is established. These include 1) the total power dissipated by the system, 2) the system logical architecture, 3) the approximate dimensions
of the chassis, and 4) the subsequent regulatory requirements for the intended market. One of the outcomes of coupling the system
architecture with the total power dissipation is the determination of the number of daughter card slots within the chassis dimension
limitations. Knowing the maximum power dissipation of the various types of daughter cards and the number desired in a system helps to
establish the constraints that limit the possible system configurations. At times, thermal constraints can directly impact the electrical
architecture of a system. This is especially true if the chassis is sized so that it places limits on the total power that can be dissipated.
A first pass formulation of a system takes place once a balance is reached between the requirements set by the system architecture
coupled with the intended market and the total power that can be dissipated within the chassis enclosure. The thermal analysis and
subsequent physical constraints on the slot pitch are required to determine the total number of daughter cards possible in the system.
Thus, the ability of a chassis to cool itself can limit the number and possibly the type of components used, including logic devices.
The design of the backplane begins in parallel to the thermal evaluation of the system, but is not set until the number of daughter card
slots and overall system configuration are established. Once the number of slots is determined, the next major step is the identification of
the type and number of signals per slot. A definition of the signaling needed in the WarpLink Reference Backplane was based on the
architecture defined by the Motorola design team. The general architecture of the WarpLink Reference Design Platform is discussed in the
Introduction
of this document.
WarpLink Backplane Physical Description
The physical configuration of the Motorola WarpLink backplane used in the reference system contains eight slots on a 1.6-inch card-to-card
pitch. The Motorola WarpLink Reference Design Platform was designed to suit both switch fabric and mesh architectures. The logical
configuration of the backplane defines slots 1 through 6 as pin-compatible Line Card slots, and slots 7 and 8 as pin-compatible Switch/Line
Card slots. When a switch fabric is inserted into slot 7, 8, or both, the system can function in either the fabric or mesh architecture. If a
Line Card is inserted into slot 7, 8, both, or neither, the system will operate in the mesh architecture. The ability of the WarpLink to do this
is due to the primary and redundant serial I/O characteristics of the device.
The signal allocations for each slot type are detailed below in Table 1.
Table 1. Signal Allocations
Signal Types
Slot 1 - 6
(Line Card)
Slot 7 - 8
(Switch/Line Card)
Signal Speed
Differential Gigabit Serial Links (Mesh/Fabric)
32 pairs
96 pairs
3.125 Gbd
Differential Clocks
2 pairs
8 pairs
156 MHz
Single-ended Address/Data/Control Busses
36 pins
36 pins
<50 MHz
The signal speed identification is critical to the design rules formulated for the layout of a gigabit backplane. For example, the addition of
unnecessary vias in the gigabit lines would adversely affect their signal transmission characteristics. Each via presents an impedance
discontinuity that will contribute to the distortion of the opening of the receiver input eye pattern. This can reduce available voltage
margins as well as time margins through an increase in signal jitter. Therefore, all differential routes of the WarpLink Reference Design
Platform backplane had vias placed only where absolutely needed - at the device pads and at the connectors (plated-through holes).
A number of issues were assessed in arriving at a final connector selection for the Motorola WarpLink backplane. The ERmet ZD high-
speed backplane connector was chosen for the gigabit nets for its high-frequency signal transmission characteristics and because it is side
stackable with a standard 2 mm hard metric connector. The ERmet 2 mm hard metric connector was selected for the slower speed
single-ended and differential clock nets.
F
Freescale Semiconductor, Inc.
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