參數(shù)資料
型號: BR1570
英文描述: WarpLink Reference Design Platform
中文描述: WarpLink參考設(shè)計平臺
文件頁數(shù): 21/24頁
文件大?。?/td> 492K
代理商: BR1570
The WarpLink device is clocked via the clock distribution networks originating from slot 7. (Please refer to the Clock Distribution section for
more details). The clock trigger of the TDS-8000 is also clocked with the same clock distribution network, by way of the Test Card in slot 1.
WarpLink Reference Design Platform
21
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(a) Without Equalization
(b) With Equalization
Figure 17. Active Eye Patterns Tx – Slot 8 to Rx – Slot 1
EYE DIAGRAMS FROM SLOT 8 TO SLOT 1
The interconnect between slots 8 and 1 are the longest channel in the 19" rack WarpLink Design Reference system that is not artificially
lengthened. The total length of the transmission channel in FR-4 is 18.7”. This includes 1.8” of FR-4 on the Line Card, 12.2” on the
backplane, and 4.7” on the Test Card. Without pre-emphasis/equalization, WarpLink exceeds the XAUI mask with a 5% margin. With pre-
emphasis/equalization, the WarpLink gigabit link satisfies the XAUI mask with a 9% margin. The comparison of Figure 17(a) and Figure
17(b) shows a clear benefit of pre-emphasis/equalization to the signal fidelity of the eye diagram.
EYE DIAGRAMS FROM SLOT 7 TO SLOT 1
The artificially lengthened interconnect between slots 7 and 1 presents a condition that is worse than that defined by the XAUI standard.
This is a worst case routing condition that exemplifies a routing implementation on a large backplane. The total length of the transmission
channel in FR-4 is 26.2”. This includes 1.8” of FR-4 on the Line Card, 19.7” on the backplane, and 4.7” on the Test Card. With pre-
emphasis/equalization on, WarpLink passes the XAUI mask with a 3% margin. As expected via simulation the resultant eye does not
conform to the XAUI mask with pre-emphasis/equalization disabled. Again, the comparison of Figure 18(a) and Figure 18(b) shows a clear
benefit of pre-emphasis/equalization to the signal fidelity of the eye diagram.
(a) Without Equalization
(b) With Equalization
Figure 18. Active EYE Patterns Tx – Slot 7 to Rx –Slot 1
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Freescale Semiconductor, Inc.
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