參數(shù)資料
型號(hào)： BR1570
英文描述： WarpLink Reference Design Platform
中文描述： WarpLink參考設(shè)計(jì)平臺(tái)
文件頁數(shù)： 2/24頁
文件大?。?/td> 492K
代理商： BR1570
TABLE OF CONTENTS
WarpLink Reference Design Platform
2
For More Information On This Product,
Go to: www.freescale.com
ABSTRACT...........................................................................................................................................3
INTRODUCTION...................................................................................................................................3
WarpLink 2.5 Quad Device....................................................................................................3
WarpLink Reference Design Platform Goals.........................................................................3
WarpLink Reference Design Platform Overview...................................................................4
Architectural Overview..................................................................................................4
Backplane.......................................................................................................................5
Line Card........................................................................................................................6
Switch Card....................................................................................................................6
Test Card........................................................................................................................6
DETAILED DESIGN DESCRIPTIONS.................................................................................................6
WarpLink Reference Backplane.............................................................................................6
Backplane/Chassis Design Considerations...................................................................7
WarpLink Backplane Physical Description....................................................................7
Backplane Design Rules and Layer Stackup..................................................................9
Line, Switch, and Test Cards...............................................................................................10
Daughter Cards Design Considerations.......................................................................10
Line Card and Test Card Layer Stackups.....................................................................10
WARPLINK SIGNAL INTEGRITY SIMULATION PROGRAM.......................................................11
WarpLink Gigabit Simulations.............................................................................................11
WarpLink Interconnect Impedance Profile ..........................................................................15
WarpLink Reference System Clock Simulations.................................................................16
DESCRIPTION OF PASSIVE SIGNAL INTEGRITY MEASUREMENTS.......................................17
Time Domain Reflectometry................................................................................................17
Differential Time Domain Crosstalk....................................................................................17
Eye Diagrams.......................................................................................................................17
Time Domain Test Equipment..............................................................................................18
PASSIVE MEASUREMENT RESULTS.............................................................................................18
TDR Results..........................................................................................................................18
Eye Diagram Measurement Results....................................................................................19
ACTIVE MEASUREMENT RESULTS...............................................................................................20
Test Setup............................................................................................................................20
Eye Diagrams From Slot 8 to Slot 1.....................................................................................21
Eye Diagrams From Slot 7 to Slot 1.....................................................................................21
SUMMARY AND CONCLUSIONS...................................................................................................22
ACKNOWLEDGEMENTS..................................................................................................................22
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Freescale Semiconductor, Inc.
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