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參數(shù)資料
| 型號： | BR1570 |
| 英文描述： | WarpLink Reference Design Platform |
| 中文描述： | WarpLink參考設(shè)計平臺 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 492K |
| 代理商： | BR1570 |
ABSTRACT
This paper describes the technical design process used in the development of a WarpLink
Reference Design Platform showcasing
Motorola’s WarpLink 2.5 Gbps Quad, a Serializer-Deserializer (SERDES) data interface device. The Reference Design Platform utilizes a
combination of good design practices to make it feasible to use an FR-4 backplane with standard components and fabrication processes to
realize 3.125 gigabaud (Gbd) XAUI-compliant channels.
A brief description of critical component selection is followed by a discussion of design considerations related to high-speed signal
integrity performance. The technical “Right-by-Design” process utilized by North East Systems Associates (NESA) included simulations that
were verified through measurements of the fabricated hardware. The simulation and experimental results highlight the special features of
the WarpLink 2.5 device making it possible to have 3.125 Gbd wire-speed transmissions through FR-4 PWB material.
WarpLink Reference Design Platform
3
For More Information On This Product,
Go to: www.freescale.com
INTRODUCTION
WARPLINK 2.5 QUAD DEVICE
The WarpLink 2.5 Quad device is a SERDES interface that transfers data between chips across a board, a backplane, or cables. It handles
four full-duplex redundant data links. Serial transceivers transmit and receive 8B/10B coded data at a nominal rate of 2.5 gigabits per
second (Gbps) through 3.125 Gbd links.
In the transmit direction, the near-end WarpLink device receives data on its four parallel transmit interfaces which accommodate 8-bit
uncoded or 10-bit precoded data bytes. When configured for the 8-bit mode, the device performs 8B/10B encoding on the uncoded data. It
then serializes the coded data and sends it onto the four corresponding primary serial differential transmitters. Data can be sent out on the
four redundant transmitters or on both primary and redundant transmitters simultaneously. Coded serial data comes out of each transmitter
at 3.125 Gbd wire-speed carrying 2.5 Gbps of user data through channels across a board, a backplane, or cables to far-end WarpLink
devices’ serial receivers.
In the receive direction, serial coded data coming from far-end WarpLink devices’ serial transmitters are received by the near-end device on
one of four primary or redundant serial receivers. The near-end device de-serializes the data and, if configured for the 8-bit mode, performs
8B/10B decoding. The device then sends the data out on the four corresponding parallel receive interfaces.
The WarpLink 2.5 Quad is packaged in a 324-pin PBGA, with a 19 mm x 19 mm (0.75 x 0.75 in) body and a 1 mm ball-to-ball pitch. The
device typically uses 1.8 watts. Its core and link power supply inputs require 1.8 V. The HSTL I/O power supply inputs (for the parallel and
digital I/Os) use either 1.5 V or 1.8 V.
For further detail on the WarpLink 2.5 Quad’s rich feature set, including Selectable Speed Range, Double Data Rate, 8B/10B, Link
Synchronization and Recovered Clock Mode, refer to the WarpLink 2.5 Quad User’s Manual.
WARPLINK REFERENCE DESIGN PLATFORM GOALS
With the introduction of the WarpLink SERDES family, consisting of the WarpLink Quad (1.0 Gbps), WarpLink Quad Double Data Rate (DDR)
(1.0 Gbps), and WarpLink 2.5 Quad (2.5 Gbps) devices, designing boards and backplanes capable of handling up to 3.125 Gbd channels
could prove challenging. The WarpLink Reference Design Platform was developed to assist designers in laying out the interconnection
system as well as to provide an example of a system designed with a backplane, daughter cards, and connectors that make 3.125 Gbd
channels feasible. The development work served as a learning experience for Motorola, with the aim of sharing the final outcome with
WarpLink customers.
A critical portion of the development effort centered on the simulation. In addition to simulations performed at 3.125 Gbd, simulations at
5Gbps were also carried out to give a better understanding of the current capabilities and limitations of the technology.
The platform was designed to accommodate WarpLink 2.5, as it is the fastest device in the family. FR-4 was chosen for the backplane and
boards for three reasons: 1) material availability, 2) relative lower cost when compared to other fabrication materials, and 3) most PWB
fabrication houses can process the material. Several channels were designed to be long enough to demonstrate WarpLink 2.5’s XAUI
compliance (50cm or 19.68in).
Standard available components were selected, specifically the ERNI HMZD connector, a high-density connector intended for high-speed
signaling. Motorola’s Timing Solutions devices, the MC100ES6111, the MC100EP222, the MPC9456, and the MC100EP8111, were
examples of currently available clock network distribution devices that are intended for use in such a system.
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Freescale Semiconductor, Inc.
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