- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385094 > AK4673EG (Asahi Kasei Microsystems Co.,Ltd) Stereo CODEC with MIC/HP-AMP and Touch Screen Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AK4673EG |
| 廠(chǎng)商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類(lèi)： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普- AMP及觸摸屏控制器 |
| 文件頁(yè)數(shù)： | 97/107頁(yè) |
| 文件大小： | 1171K |
| 代理商： | AK4673EG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)當(dāng)前第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)
[AK4673]
MS0670-E-00
2007/09
- 97 -
2.
PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
(Addr:01H, D0)
Internal Clock
(1)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
(2)
(3)
LRCK pin
BICK pin
(4)
(5)
Input
4fs of
“H”
Example:
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(3) Addr:00H, Data:40H
(2) Addr:04H, Data:32H
Addr:05H, Data:00H
(4) Addr:01H, Data:01H
Figure 86. Clock Set Up Sequence (2)
<Example>
(1)
After Power Up: The PDN pin “L”
“H”. “L” time of 150ns or more is needed to reset the AK4673.
The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at line output and headphone output.
(2)
DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3)
Power Up VCOM: PMVCM bit = “0”
“1”
VCOM should first be powered up before the other block operates.
(4)
PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 2ms(max)
when BICK is a PLL reference clock.
(5)
Normal operation stats after that the PLL is locked.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4682 | Multi-channel CODEC with 2Vrms Stereo Selector |
| AK4682EQ | Multi-channel CODEC with 2Vrms Stereo Selector |
| AK4683_07 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4675 | 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP |
| AK4675EG | 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP |
| AK4682 | 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Multi-channel CODEC with 2Vrms Stereo Selector |
| AK4682AEQ | 功能描述:IC CODEC MULTI-CHANNEL 48LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
| AK4682EQ | 制造商:AKM 制造商全稱(chēng):AKM 功能描述:Multi-channel CODEC with 2Vrms Stereo Selector |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。