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參數(shù)資料
| 型號： | AK4673EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普- AMP及觸摸屏控制器 |
| 文件頁數(shù)： | 35/107頁 |
| 文件大小： | 1171K |
| 代理商： | AK4673EG |
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[AK4673]
MS0670-E-00
2007/09
- 35 -
■
System Reset
When power-up, the AK4673 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is
“0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data
outputs of both channels are forced to a 2’s compliment, “0”. The ADC output reflects the analog input signal after the
initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.
The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are
“0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2’s compliment, “0”. The DAC output reflects the digital input data after
the initialization cycle is complete. When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle.
■
Audio Interface Format
Four types of data formats are available and are selected by setting the DIF1-0 bits (
Table 17
). In all modes, the serial data
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and
BICK are output from the AK4673 in master mode, but must be input to the AK4673 in slave mode.
Mode
DIF1 bit
DIF0 bit
SDTO (ADC)
0
0
0
DSP Mode
1
0
1
MSB justified
LSB justified
2
1
0
MSB justified
MSB justified
3
1
1
I
2
S compatible
I
2
S compatible
Table 17. Audio Interface Format
In Modes 1-3, the SDTO is clocked out on the falling edge (“
↓
”) of BICK and the SDTI is latched on the rising edge
(“
↑
”).
In Mode 0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (
Table 18
).
MSB
S
MSB of SDTO is output by the rising edge (“
↑
”) of the first
BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the falling edge (“
↓
”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by the falling edge (“
↓
”) of the first
BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the rising edge (“
↑
”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next rising edge (“
↑
”) of the falling
edge (“
↓
”) of the first BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the falling edge (“
↓
”) of the BICK
just after the output timing of SDTO’s MSB.
MSB of SDTO is output by next falling edge (“
↓
”) of the rising
edge (“
↑
”) of the first BICK after the rising edge (“
↑
”) of LRCK.
MSB of SDTI is latched by the rising edge (“
↑
”) of the BICK
just after the output timing of SDTO’s MSB.
Table 18. Audio Interface Format in Mode 0
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “
1” at 16bit data is converted to “
1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “
1” at 8-bit data will be converted to “
256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
SDTI (DAC)
DSP Mode
BICK
≥
32fs
≥
32fs
≥
32fs
≥
32fs
Figure
Table 18
Figure 28
Figure 29
Figure 30
(default)
DIF1
DIF0
BCKP
Audio Interface Format
Figure
0
0
Figure 24
(default)
0
1
Figure 25
1
0
Figure 26
0
0
1
1
Figure 27
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