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參數(shù)資料
| 型號： | AK4673EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普- AMP及觸摸屏控制器 |
| 文件頁數(shù)： | 96/107頁 |
| 文件大小： | 1171K |
| 代理商： | AK4673EG |
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[AK4673]
MS0670-E-00
2007/09
- 96 -
CONTROL SEQUENCE
■
Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1.
PLL Master Mode.
BICK pin
LRCK pin
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
40msec(max)
Output
(1)
(6)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
(2)
(3)
MCKI pin
(5)
(4)
Input
M/S bit
(Addr:01H, D3)
MCKO pin
Output
(8)
(7)
40msec(max)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 8kHz
(1) Power Supply & PDN pin = “L”
“H”
(3)Addr:00H, Data:40H
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:00H
(4)Addr:01H, Data:0BH
MCKO, BICK and LRCK output
Figure 85. Clock Set Up Sequence (1)
<Example>
(1)
After Power Up, the PDN pin = “L”
“H”. “L” time of 150ns or more is needed to reset the AK4673.
The AK4673 should be operated by the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at line output and headphone output.
(2)
DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3)
Power UpVCOM: PMVCM bit = “0”
“1”
VCOM should first be powered-up before the other block operates.
(4)
In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5)
PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6)
The AK4673 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7)
The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8)
The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
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