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參數資料
| 型號： | AK4516AVF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 3V 16BIT ADC&DAC WITH BUILT-IN PGA |
| 中文描述： | 3V的16位ADC |
| 文件頁數： | 26/39頁 |
| 文件大?。?/td> | 355K |
| 代理商： | AK4516AVF |
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ASAHI KASEI
[AK4516A]
M0026-E-00
1998/08
- 26 -
LTM1-0:Zero crossing timeout(ZELM="1") or Update period(ZELM="0") at the auto limitter mode
(LTM1="1", LTM0="0"@RESET)
Zero crossing timeout(ZELM="1")
48kHz
44.1kHz
129/fs
2.7ms
258/fs
5.4ms
516/fs
10.8ms
1032/fs
21.5ms
Table 6 . Zero crossing timeout or Update period at the auto limitter mode
Update period(ZELM="0")
48kHz
44.1kHz
21us
42us
83us
167us
LTM1
LTM0
32kHz
4.0ms
8.1ms
16.1ms
32.3ms
32kHz
31us
63us
125us
250us
0
0
1
1
0
1
0
1
2.9ms
5.9ms
11.7ms
23.4ms
1/fs
2/fs
4/fs
8/fs
23us
45us
91us
181us
ZELM: Enables zero crossing detection at the auto limitter operation (0: Disable, 1: Enable)
0: The IPGA value is changed immediately. When the IPGA value is changed continuously,
the change is done by the period specified by LTM1-0.
1: When IPGA of each L/R channel do zero crossing or timeout independently, the IPGA
value is changed by auto limitter operation.
These bits are reset by PD pin="L", then inhibits writing to these bits.
Peak Hold
Addr Register Name
04H Peak Hold Low Byte Lch
05H Peak Hold High Byte Lch
06H Peak Hold Low Byte Rch
07H Peak Hold High Byte Rch
D7
PLL7
PUL7
PLR7
PUR7
D6
PLL6
PUL6
PLR6
PUR6
D5
PLL5
PUL5
PLR5
PUR5
D4
PLL4
PUL4
PLR4
PUR4
D3
PLL3
PUL3
PLR3
PUR3
D2
PLL2
PUL2
PLR2
PUR2
D1
PLL1
PUL1
PLR1
PUR1
D0
PLL0
PUL0
PLR0
PUR0
R/W
RESET
RD
00H
PLL7-0:
PUL7-0:
PLR7-0:
PUR7-0:
Peak hold of Lch (Absolute value), 8bit of LSB (FFH
～
00H)
Peak hold of Lch (Absolute value), 8bit of MSB (7FH
～
00H)
Peak hold of Rch (Absolute value), 8bit of LSB (FFH
～
00H)
Peak hold of Rch (Absolute value), 8bit of MSB (7FH
～
00H)
The peak is held L/R audio data independently. These registers are reset by reading 8bit of MSB, reading 8bit
of both MSB and LSB should be continuity controlled by reading in order of 8 bit of MSB from LSB. After
reading the 8 bit of LSB the last, 8 bit of MSB is lost by reading 8 bit of LSB the last. Sign bits (PUL7, PUR7)
becomes "0" as the output value is the absolute value.
These registers are reset on the following any conditions.
PD
pin="L"
PM1="0"
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