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參數(shù)資料
| 型號： | AK4516AVF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 3V 16BIT ADC&DAC WITH BUILT-IN PGA |
| 中文描述： | 3V的16位ADC |
| 文件頁數(shù)： | 14/39頁 |
| 文件大小： | 355K |
| 代理商： | AK4516AVF |
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ASAHI KASEI
[AK4516A]
M0026-E-00
1998/08
- 14 -
Control Register R/W Timing
The data on the 4 wires serial interface consists of op-code(3bit), address(LSB-first, 5bit) and control data
(LSB-first, 8bit). The transmitting data is output to each bit by "
↓
" of CCLK, the receiving data is latched by "
↑
"
of CCLK. Writing data becomes effective by "
↑
" of CS. Reading data becomes Hi-Z(floating) by "
↑
" of CS.
CS should be held to "H" at no access. In case of connecting between CDTI and CDTO, the I/F can be also
controlled by 3-wires.
CCLK always needs 16 edges of "
↑
" during
CS
="L". Reading/Writing of the address except 00H
～
0DH are
inhibited.
Reading/Writing of the control registers by except op0=op1="1" are invalid.
op0- op2: Op- code (111:WRITE, 110:READ)
A0- A4:
Address
D0- D7:
Control Data
Figure 5 . Control Data Timing
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