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參數(shù)資料
| 型號： | AK4516AVF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 3V 16BIT ADC&DAC WITH BUILT-IN PGA |
| 中文描述： | 3V的16位ADC |
| 文件頁數(shù)： | 11/39頁 |
| 文件大?。?/td> | 355K |
| 代理商： | AK4516AVF |
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ASAHI KASEI
[AK4516A]
M0026-E-00
1998/08
- 11 -
OPERATION OVERVIEW
System Clock
The clocks which are required to operate are MCLK(256fs/384fs), LRCK(fs), BCLK(32fs
～
). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3
automatically. *fs is sampling frequency.
All external clocks (MCLK, BCLK, LRCK) should always be present whenever IPGA or ADC or DAC is in operation.
If these clocks are not provided, the AK4516A may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4516A should be in
the power-down mode. (Please refer to the "Mode Control 1" section.)
System Reset
AK4516A should be reset once by bringing
PD
pin "L" upon power-up. The internal timing starts clocking by LRCK
"
↑
" after exiting reset by MCLK. After the system reset operation, the all internal AK4516A registers are initial value.
Zero detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF
immediately goes to "L", if the input data are not zero. When the DAC is power-down, DZF becomes to "L".
Digital High Pass Filter(HPF)
The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.4Hz(@fs=44.1kHz) and it is -0.1dB at
22Hz. It also scales with the sampling frequency(fs).
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