參數(shù)資料
型號: AK4371
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: DAC with built-in PLL & HP-AMP
中文描述: DAC,帶有內置的鎖相環(huán)
文件頁數(shù): 59/62頁
文件大?。?/td> 842K
代理商: AK4371
[AK4371]
MS0596-E-00
2007/04
- 59 -
SYSTEM DESIGN
Figure 45 shows the system connection diagram. An evaluation board [AKD4371] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
Analog Supply
1.6
3.6V
0.1μ
16
Ω
220μ
+
220μ
+
16
Ω
Headphone
10
0.1μ
+ 10μ
2.2μ
+
Speaker
SPK-Amp
Cp
Rp
Audio Controller
μP
1
HPR
HPL
RIN2
LIN2
RIN3
LIN3
RIN1
LIN1
V
H
A
V
V
R
L
M
S
B
L
M
D
P
V
V
MUTET
I2C
PDN
CSN
CCLK
CDTI
MCKO
VSS3
AK4371VN
Top View
25
26
27
28
29
30
31
32
2
2
2
1
16
15
14
13
12
11
10
9
2
2
1
1
1
2
3
4
5
6
7
8
0.22μ
Handsfree
Analog Ground
Digital Ground
0
0
Notes:
- VSS1, VSS2 and VSS3 of the AK4371 should be distributed separately from the ground of external controllers.
- All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must
not be left floating.
- When the AK4371 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin is not needed.
- When the AK4371 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin should be
connected as shown in Table 4
- When the AK4371 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to
“1”. Therefore, a 100k
Ω
pull-up resistor should be connected to the LRCK and BICK pins of the AK4371.
- When DVDD is supplied from AVDD via 10
Ω
series resistor, the capacitor larger than 0.1
μ
F should not be
connected between DVDD and the ground.
Figure 45. Typical Connection Diagram (In case of AC coupling to MCKI)
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AK4371VN DAC with built-in PLL & HP-AMP
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相關代理商/技術參數(shù)
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