參數(shù)資料
型號(hào)： AK4371
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁數(shù)： 41/62頁
文件大?。?/td> 842K
代理商： AK4371
[AK4371]
MS0596-E-00
2007/04
- 41 -
4) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
→
HP-Amp
Power Supply
PDN pin
PMVCM bit
HPL/R pins
(6)
(6)
(7)
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(4)
(Hi-Z)
(Hi-Z)
PMHPL/R bits
Don’t care
(1) >150ns
(2) >0s
MUTEN bit
LIN1HL, LIN2HL, LIN3HL
RIN1HR, RIN2HR, RIN3HL bits
(3) >0s
(5) >2ms
(5) >2ms
Figure 32. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and HP-Amp
(1)
When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be
stopped when DAC is not used.
(2)
PMVCM bit should be changed to “1” after PDN pin goes “H”.
(3)
LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits should be changed to “1” after PMVCM bit is
changed to “1”.
(4)
When LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR or RIN3HR bit is changed to “1”, LIN1, RIN1, LIN2, RIN2,
LIN3 or RIN3 pin is biased to 0.475 x AVDD.
(5)
PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin
is 2.2
μ
F) after LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits are changed to “1”.
(6)
Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t
r
= 70k x C(typ). When C=1
μ
F, t
r
= 70ms(typ).
(7)
Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t
f
= 60k x C(typ). When C=1
μ
F, t
f
= 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to VSS1. After that, the LIN1HL,
LIN2HL, LIN3HL, RIN1HR, RIN2HR and RIN3HR bits should be changed to “0”.
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