參數(shù)資料
型號(hào): AK4371
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: DAC with built-in PLL & HP-AMP
中文描述: DAC,帶有內(nèi)置的鎖相環(huán)
文件頁數(shù): 33/62頁
文件大?。?/td> 842K
代理商: AK4371
[AK4371]
MS0596-E-00
2007/04
- 33 -
< Analog Mixing Circuit for Headphone Output >
DALHL, LIN1HL, RIN1HL, LIN2HL, RIN2HL, LIN3HL and RIN3HL bits control each path switch of HPL output.
DARHR, LIN1HR, RIN1HR, LIN2HR, RIN2HR, LIN3HR and RIN3HR bits control each path switch of HPR output.
When L1HM=L2HM=L3HM bits = “0”, HPG1-0 bits = “00” (R
1H
= R
2H
= R
3H
= R
DH
= 100k) and ATTH4-0 bits =
“00H”(0dB), the mixing gain is +0.95dB(typ). When HPG1-0 bit = “01” (R
DH
= 50k), the mixing gain of DAC path is
+6.95dB(typ). When HPG1-0 bit = “10” (R
DH
= 25k), the mixing gain of DAC path is +12.95dB(typ). When L1HM,
L2HM and L3HM bits are “1”, LIN1/RIN1, LIN2/RIN2 and LIN3/RIN3 signals are output from HPL/R pins as (L+R)/2
respectively (R
1H
= R
2H
= R
3H
= 200k).
When LDIF=LDIFH=LIN1L=RIN1R bits = “1”, LIN1 and RIN1 pins becomes IN
and IN+ pins, respectively. IN+ and
IN
pins can be used as full-differential mono line input for analog mixing for headphone-amp. In this case, LIN1HL,
RIN1HL, LIN1HR and RIN1HR bits should be “0”.
If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM
voltage (= 0.475 x AVDD) externally. Figure 46 shows the external bias circuit example.
Figure 27
LDIFH bit
+
HPL pin
RIN3 pin
HP-Amp
1.11R
H
R
DH
R
3H
RIN3HL bit
DALHL bit
+
100k(typ)
R
H
RIN2 pin
LIN3 pin
R
3H
R
2H
RIN2HL bit
LIN3HL bit
LIN2 pin
R
2H
LIN2HL bit
DAC Lch
RIN1 pin
R
1H
RIN1HL bit
LIN1 pin
R
1H
LIN1HL bit
100k(typ)
+
HPR pin
RIN3 pin
HP-Amp
1.11R
H
R
DH
R
3H
RIN3HR bit
DARHR bit
+
100k(typ)
R
H
RIN2 pin
LIN3 pin
R
3H
R
2H
RIN2HR bit
LIN3HR bit
LIN2 pin
R
2H
LIN2HR bit
DAC Rch
RIN1 pin
R
1H
RIN1HR bit
LIN1 pin
R
1H
LIN1HR bit
Figure 27
100k(typ)
LDIFH bit
Figure 25. Summation circuit for HPL/R output
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