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參數(shù)資料
| 型號： | AK4371 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 18/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371 |
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[AK4371]
MS0596-E-00
2007/04
- 18 -
OPERATION OVERVIEW
■
System Clock
There are the following six clock modes to interface with external devices (Table 1 and Table 2).
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 11
1
0
See Table 4
Figure 12
1
0
See Table 4
Figure 13
1
0
See Table 4
Figure 14
0
0
1
0
x
x
Figure 15
Figure 16
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
BICK pin
Output
(Selected by
BF bit)
LRCK pin
Selected by
PLL4-0 bits
Output
(1fs)
0
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
Selected by
PLL4-0 bits
Input
(32fs
～
64fs)
Input
(1fs)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
0
“L”
GND
Input
(Selected by
PLL4-0 bits)
Input
(32fs
～
64fs)
Output
(Selected by
BF bit)
Input
(32fs
～
64fs)
Input
(1fs)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
0
“L”
GND
Input
(1fs)
EXT Master Mode
0
“L”
Selected by
FS3-0 bits
Output
(1fs)
EXT Slave Mode
0
“L”
Selected by
FS3-0 bits
Input
(1fs)
Table 2. Clock pins state in Clock Mode
■
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4371 is power-down mode (PDN pin = “L”) and exits reset state, the AK4371 is slave mode. After exiting reset state,
the AK4371 goes to master mode by changing M/S bit = “1”.
When the AK4371 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK4371 should be pulled-down or pulled-up by the resistor (about 100k
Ω
) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
(default)
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4371VN | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372 | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372ECB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372VCB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4373 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
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