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參數(shù)資料
| 型號(hào)： | AK4371 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁(yè)數(shù)： | 13/62頁(yè) |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371 |
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[AK4371]
MS0596-E-00
2007/04
- 13 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD, PVDD, HVDD=1.6
～
3.6V; C
L
= 20pF; unless otherwise specified)
Parameter
Master Clock Input Timing
Frequency (PLL mode)
(EXT mode)
Pulse Width Low (Note 24)
Pulse Width High (Note 24)
AC Pulse Width (Note 25)
LRCK Timing
Frequency
Duty Cycle: Slave Mode
Master Mode
MCKO Output Timing (PLL mode)
Frequency
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
(fs=32kHz, PS1-0= “00”)
Serial Interface Timing
(Note 26)
Slave Mode (M/S bit = “0”):
BICK Period (Note 27)
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
(PLL Mode, PLL4-0 bits = “EH”)
(PLL Mode, PLL4-0 bits = “EH”)
BICK Pulse Width Low
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
BICK Pulse Width High
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
LRCK Edge to BICK “
↑
” (Note 28)
BICK “
↑
” to LRCK Edge (Note 28)
SDATA Hold Time
SDATA Setup Time
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
BICK Duty
BICK “
↓
” to LRCK
SDATA Hold Time
SDATA Setup Time
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
↑
” to CCLK “
↑
”
CCLK “
↑
” to CSN “
↑
”
Note 24. Except AC coupling.
Note 25. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground. Refer to Figure 3.
Note 26. Refer to “Serial Data Interface”.
Note 27. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
Symbol
fCLK
fCLK
tCLKL
tCLKH
tACW
fs
Duty
Duty
fCLKO
dMCK
dMCK
min
11.2896
2.048
0.4/fCLK
0.4/fCLK
18.5
8
45
-
0.256
40
-
typ
-
-
-
-
-
44.1
-
50
-
-
33
max
27
24.576
-
-
-
48
55
-
12.288
60
-
Units
MHz
MHz
ns
ns
ns
kHz
%
%
MHz
%
%
tBCK
tBCK
tBCK
tBCKL
tBCKL
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
fBCK
fBCK
dBCK
tMBLR
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
312.5 or 1/(64fs)
-
-
100
0.4 x tBCK
100
0.4 x tBCK
50
50
50
50
-
-
-
50
50
50
200
80
80
40
40
150
50
50
-
1/(32fs)
-
-
-
-
-
-
-
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/(32fs)
1/(64fs)
-
-
-
-
-
-
-
-
64fs
32fs
50
-
-
-
-
-
-
-
-
-
-
-
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