參數(shù)資料
型號(hào)： AK4371
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁(yè)數(shù)： 22/62頁(yè)
文件大小： 842K
代理商： AK4371
[AK4371]
MS0596-E-00
2007/04
- 22 -
■
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the
AK4371 is generated by an internal PLL circuit. Input frequency is selected by PLL4-0 bits (Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4371 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC should be in the
power-down mode (PMDAC bits = “0”).
AK4371
DSP or
μ
P
MCKO
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKI
1fs
32fs ~ 64fs
256fs/128fs/64fs/32fs
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
MCLK
Figure 12. PLL Slave Mode (PLL Reference Clock: MCKI pin)
b) PLL reference clock: BICK pin
Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4371
DSP or
μ
P
MCKO
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKI
1fs
32fs or 64fs
Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin)
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