- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385091 > AK4371 (Asahi Kasei Microsystems Co.,Ltd) DAC with built-in PLL & HP-AMP PDF資料下載
參數(shù)資料
| 型號： | AK4371 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內置的鎖相環(huán) |
| 文件頁數(shù)： | 19/62頁 |
| 文件大?。?/td> | 842K |
| 代理商： | AK4371 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
[AK4371]
MS0596-E-00
2007/04
- 19 -
■
PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL lock time is shown in Table 4, whenever the AK4371 is
supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0”
→
“1”) or sampling frequency changes.
1)
Setting of PLL Mode
Mode
2
R,C at VCOC
R[
Ω
]
PLL4 PLL3
PLL
PLL1 PLL0
Reference Clock
fs
(Note
32)
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 3
Type 4
Table 6
Table 6
Table 6
C[F]
PLL Lock
Time (typ)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
BICK
BICK
LRCK
N/A
11.2896MHz
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
26MHz
27MHz
13MHz
26MHz
19.8MHz
27MHz
32fs
64fs
fs
10k
10k
10k
10k
10k
15k
10k
10k
15k
10k
10k
10k
10k
10k
6.8k
6.8k
6.8k
22n
22n
47n
22n
22n
330n
47n
47n
330n
47n
22n
22n
22n
22n
47n
47n
330n
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
20ms
20ms
20ms
20ms
20ms
20ms
80ms
(default)
Others Others
Note 32. Refer to Table5 about Type1-4
Note 33 : Clock jitter is lower in Mode10 ~13 than Mode5, 7, 8 and 9, respectively.
Note 34. Modes 14~16 are available at Slave Mode only.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2)
Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
fs
(default)
Mode
FS3 FS2 FS1 FS0
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
48.0007kHz
24.0004kHz
12.0002kHz
32.0005kHz
16.0002kHz
8.0001kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 3
47.9992kHz
23.9996kHz
11.9998kHz
31.9994kHz
15.9997kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 4
47.9997kHz
23.9999kHz
11.9999kHz
31.9998kHz
15.9999kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
0
1
2
4
5
6
8
9
10
3, 7,
11-15
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
Others
N/A
N/A
N/A
N/A
Table 5. Setting of Sampling Frequency (PLL reference clock input is MCKI pin)
相關PDF資料 |
PDF描述 |
|---|---|
| AK4371VN | DAC with built-in PLL & HP-AMP |
| AK4380 | 100dB 24 Bit 96KHz 2ch DAC(100dB的動態(tài)范圍，采樣率96KHz的24位音頻D/A轉換器) |
| AK4380VT | 100dB 24BIT 96kHz 2CH DAC |
| AK4382A | 112dB 192kHz 24-Bit 2ch DAC |
| AK4382 | 112dB 192kHz 24-BIT SCH DAC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4371VN | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372 | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372ECB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4372VCB | 制造商:AKM 制造商全稱:AKM 功能描述:DAC with built-in PLL & HP-AMP |
| AK4373 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Stereo DAC with HP/SPK-Amp |
發(fā)布緊急采購，3分鐘左右您將得到回復。