參數(shù)資料
型號(hào)： AK4371
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內(nèi)置的鎖相環(huán)
文件頁(yè)數(shù)： 49/62頁(yè)
文件大?。?/td> 842K
代理商： AK4371
[AK4371]
MS0596-E-00
2007/04
- 49 -
■
Register Definitions
Addr Register Name
00H
Power Management 0
R/W
Default
PMVCM: Power Management for VCOM Block
0: Power OFF (default)
1: Power ON
PMDAC: Power Management for DAC Blocks
0: Power OFF (default)
1: Power ON
When the PMDAC bit is changed from “0” to “1”, the DAC is powered-up to the current register values
(ATT value, sampling rate, etc).
PMHPL: Power Management for the left channel of the headphone-amp
0: Power OFF (default). HPL pin goes to VSS1(0V).
1: Power ON
PMHPR: Power Management for the right channel of the headphone-amp
0: Power OFF (default). HPR pin goes to VSS1(0V).
1: Power ON
MUTEN: Headphone Amp Mute Control
0: Mute (default). HPL and HPR pins go to VSS1(0V).
1: Normal operation. HPL and HPR pins go to 0.475 x AVDD.
PMLO: Power Management for Stereo Output
0: Power OFF (default) LOUT/ROUT pins go to Hi-Z.
1: Power ON
PMPLL: Power Management for PLL
0: Power OFF: EXT mode (default)
1: Power ON: PLL mode
PMVREF: Power Management for VREF
0: Power OFF (default)
1: Power ON
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”,
all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default
value.
When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMMO, PMPLL, PMVREF and MCKO bits are “0”, all
blocks are powered-down. The register values remain unchanged. Power supply current is 20
μ
A(typ) in this case.
For fully shut down (typ. 1
μ
A), PDN pin should be “L”.
D7
D6
D5
D4
D3
D2
D1
D0
PMVREF
PMPLL
R/W
0
PMLO
R/W
0
MUTEN
R/W
0
PMHPR
R/W
0
PMHPL
R/W
0
PMDAC
R/W
0
PMVCM
R/W
0
R/W
0
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