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ADV7344
MPU PORT TIMING SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V. PV
DD
= 1.71 V to 1.89 V. V
AA
= 2.6 V to 3.465 V. V
DD_IO
= 2.97 V to 3.63 V.
All specifications T
MIN
to T
MAX
(40°C to +85°C), unless otherwise noted.
Rev. 0 | Page 8 of 88
Table 8.
Parameter
MPU PORT, I
2
C MODE
1
SCL Frequency
SCL High Pulse Width, t
1
SCL Low Pulse Width, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDA, SCL Rise Time, t
6
SDA, SCL Fall Time, t
7
Setup Time (Stop Condition), t
8
MPU PORT, SPI MODE
1
SCLK Frequency
SPI_SS to SCLK Setup Time, t
1
SCLK High Pulse Width, t
2
SCLK Low Pulse Width, t
3
Data Access Time after SCLK Falling Edge, t
4
Data Setup Time prior to SCLK Rising Edge, t
5
Data Hold Time after SCLK Rising Edge, t
6
SPI_SS to SCLK Hold Time, t
7
SPI_SS to MISO High Impedance, t
8
1
Guaranteed by characterization.
POWER SPECIFICATIONS
Conditions
See Figure 19.
Min
0
0.6
1.3
0.6
0.6
100
0.6
0
20
50
50
20
0
0
Typ
Max
400
300
300
10
35
40
Unit
kHz
μs
μs
μs
μs
ns
ns
ns
μs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
See Figure 20.
Table 9.
Parameter
NORMAL POWER MODE
1, 2
I
DD3
I
DD_IO
I
AA5
I
PLL
SLEEP MODE
I
DD
I
AA
I
DD_IO
I
PLL
1
R
SET1
= 510 Ω (DAC 1, DAC 2 and DAC 3 operating in full drive mode). R
SET2
= 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
2
75% color bar test pattern applied to pixel data pins.
3
I
DD
is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
I
AA
is the total current required to supply all DACs including the V
REF
circuitry.
Conditions
SD only (16× oversampling)
ED only (8× oversampling)
4
HD only (4× oversampling)
4
SD (16× oversampling) and ED (8× oversampling)
SD (16× oversampling) and HD (4× oversampling)
3 DACs enabled (ED/HD only)
6 DACs enabled (SD only and simultaneous modes )
SD only, ED only or HD only modes
Simultaneous modes
Min
Typ
90
65
91
95
122
1
124
140
5
10
5
0.3
0.2
0.1
Max
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA