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參數(shù)資料
| 型號： | ADV7344BSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| 中文描述： | SERIAL INPUT LOADING, 14-BIT DAC, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 51/88頁 |
| 文件大?。?/td> | 1078K |
| 代理商： | ADV7344BSTZ |
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ADV7344
Typical F
SC
Values
Table 38 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
Rev. 0 | Page 51 of 88
Table 38. Typical F
SC
Values
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
F
SC
0
F
SC
1
F
SC
2
F
SC
3
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV7344 supports a SD noninterlaced mode. Using this
mode, progressive inputs at twice the frame rate of NTSC and
PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input
into the ADV7344. The SD noninterlaced mode can be enabled
using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the S_HSYNC and
S_VSYNC pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD
noninterlaced mode.
For 240p/59.94 Hz input, the ADV7344 should be configured for
NTSC operation, and Subaddress 0x88, Bit 1 should be set to 1.
For 288p/50 Hz input, the ADV7344 should be configured for
PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7344 can be used to operate in square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. Alternatively, for PAL operation, an input
clock of 29.5 MHz is required. The internal timing logic adjusts
accordingly for square pixel mode operation. In square pixel mode,
the timing diagrams shown in Figure 63 and Figure 64 apply.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
YC
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
0
Figure 63. Square Pixel Mode EAV/SAV Embedded Timing
FIELD
PIXEL
DATA
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Cb
Y
Cr
Y
HSYNC
0
Figure 64. Square Pixel Mode Active Pixel Timing
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