參數(shù)資料
型號(hào)： ADV7344BSTZ
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs
中文描述： SERIAL INPUT LOADING, 14-BIT DAC, PQFP64
封裝： ROHS COMPLIANT, MS-026BCD, LQFP-64
文件頁數(shù)： 33/88頁
文件大小： 1078K
代理商： ADV7344BSTZ
ADV7344
Table 20. Register 0x34 to Register 0x35
SR7 to
SR0
Register
0x34
ED/HD Mode
Register 5
Rev. 0 | Page 33 of 88
Bit Description
ED/HD Timing Reset.
Bit Number
5
4
0
1
0
Register Setting
Internal ED/HD timing counters enabled.
Resets the internal ED/HD timing counters.
HSYNC output control.
VSYNC output control.
P_BLANK active high.
P_BLANK active low.
Macrovision disabled.
Macrovision enabled.
0 must be written to this bit.
Reset
Value
0x48
7
6
3
0
1
2
0
1
1
0
1
0
0
1
ED/HD HSYNC Control.
1
ED/HD VSYNC Control.
1
ED/HD Blank Polarity.
ED Macrovision Enable.
Reserved.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0 = field input.
1 = VSYNC input.
Update field/line counter.
Field/line counter free running.
Disabled.
Enabled.
Disabled.
Enabled.
DAC 2 = Pb, DAC 3 = Pr.
DAC 2 = Pr, DAC 3 = Pb.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
Enabled.
Mode A.
Mode B.
Disabled.
Enabled.
ED/HD VSYNC/Field Input.
Horizontal/Vertical Counters.
2
Reserved.
ED/HD RGB Input Enable.
0x00
ED/HD Sync on PrPb.
ED/HD Color DAC Swap.
ED/HD Gamma Correction
Curve Select.
ED/HD Gamma Correction
Enable.
ED/HD Adaptive Filter Mode.
0x35
ED/HD Mode
Register 6
ED/HD Adaptive Filter Enable.
1
Used in conjunction with ED/HD Sync in Subaddress 0x02, Bit 7, set to 1.
2
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
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