參數(shù)資料
型號： ADUC7121BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 86/96頁
文件大?。?/td> 0K
描述： IC ARM7TDMI MCU 126KB 108CSPBGA
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 托盤
Data Sheet
ADuC7121
Rev. B | Page 87 of 96
Table 125. Timer0 Interface MMRs
Name
Description
T0LD
16-bit register that holds the 16-bit value
loaded into the counter. Available only in
16-bit mode.
T0CAP
16-bit register that holds the 16-bit value
captured by an enabled IRQ event. Available
only in 16-bit mode.
T0VAL0/T0VAL1
TOVAL0 is a 16-bit register that holds the 16
least significant bits (LSBs).
T0VAL1 is a 32-bit register that holds the 32
most significant bits (MSBs).
T0VAL0 and T0VAL1 are read only. In 16-bit
mode, 16-bit T0VAL0 is used. In 48-bit mode,
both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
T0ICLR
8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit
mode.
T0CON
Configuration MMR.
Timer0 Value Registers
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold
the 16 least significant bits and 32 most significant bits, respectively.
T0VAL0 and T0VAL1 are read-only registers. In 16-bit mode,
16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0
and 32-bit T0VAL1 are used.
Name:
T0VAL0
Address:
0xFFFF0304
Default value: 0x0000
Access:
Read only
Name:
T0VAL1
Address:
0xFFFF0308
Default value: 0x00000000
Access:
Read only
Timer0 Capture Register
This is a 16-bit register that holds the 16-bit value captured by
an enabled IRQ event; available in 16-bit mode only.
Name:
T0CAP
Address:
0xFFFF0314
Default value: 0x0000
Access:
Read only
Timer0 Control Register
This 17-bit MMR configures the mode of operation of Timer0.
Name:
T0CON
Address:
0xFFFF030C
Default value: 0x00000000
Access:
Read and write
Table 126. T0CON MMR Bit Designations
Bit
Value
Description
31:18
Reserved.
17
Event select bit.
Set by the user to enable time capture of an
event.
Cleared by the user to disable time capture of
an event.
16:12
Event select range, 0 to 16. The events are
described in the introduction to the Timers
section.
11
Reserved.
10:9
Clock select.
00
Internal 32 kHz oscillator.
01
UCLK.
10
External 32 kHz crystal.
11
HCLK.
8
Count up. Available in 16-bit mode only.
Set by the user for Timer0 to count up.
Cleared by the user for Timer0 to count down
(default).
7
Timer0 enable bit.
Set by the user to enable Timer0.
Cleared by the user to disable Timer0
(default).
6
Timer0 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default).
5
Reserved.
4
Timer0 mode of operation.
0
16-bit operation (default).
1
48-bit operation.
3:0
Prescaler.
0000
Source clock divide-by-1 (default).
0100
Source clock divide-by-16.
1000
Source clock divide-by-256.
1111
Source clock divide-by-32,768.
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