參數(shù)資料
型號(hào): ADUC7121BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 58/96頁
文件大?。?/td> 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 126KB(63K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤
Data Sheet
ADuC7121
Rev. B | Page 61 of 96
UART Interrupt Enable Register 0
This 8-bit register enables and disables the individual UART
interrupt sources.
Name:
COMIEN0
Address:
0xFFFF0804
Default value: 0x00
Access:
Read and write
Table 86. COMIEN0 MMR Bit Designations
Bit
Name
Description
7 to 3
Reserved. Not used.
Cleared by the user.
2
ELSI
Receive pin (SIN) status interrupt enable
bit.
Set by the user to enable generation of
an interrupt if any of the COMSTA0[3:1]
register bits are set.
Cleared by the user.
1
ETBEI
Enable transmit buffer empty interrupt.
Set by the user to enable an interrupt
when the buffer is empty during a
transmission, that is, when COMSTA[5]
is set.
Cleared by the user.
0
ERBFI
Enable receive buffer full interrupt.
Set by the user to enable an interrupt
when the buffer is full during a
reception.
Cleared by the user.
UART Interrupt Identification Register 0
This 8-bit register reflects the source of the UART interrupt.
Name:
COMIID0
Address:
0xFFFF0808
Default value: 0x01
Access:
Read only
Table 87. COMIID0 MMR Bit Designations
Bits[2:1]
Status
Bits
Bit 0
NINT
Priority
Definition
Clearing
Operation
00
1
No interrupt
11
0
1
Receive line
status
interrupt
Read
COMSTA0
10
0
2
Receive
buffer full
interrupt
Read COMRX
01
0
3
Transmit
buffer empty
interrupt
Write data to
COMTX or
read COMIID0
00
0
4
Modem
status
interrupt
Read
COMSTA1
register
UART Fractional Divider Register
This 16-bit register controls the operation of the fractional
divider for the ADuC7121.
Name:
COMDIV2
Address:
0xFFFF082C
Default value: 0x0000
Access:
Read and write
Table 88. COMDIV2 MMR Bit Designations
Bit
Name
Description
15
FBEN
Fractional baud rate generator enable bit.
Set by the user to enable the fractional
baud rate generator.
Cleared by the user to generate the baud
rate using the standard 450 UART baud rate
generator.
14:13
Reserved.
12:11
FBM[1:0]
M. If FBM = 0, M = 4. See Equation 2 for the
calculation of the baud rate using a
fractional divider and Table 82 for common
baud rate values.
10:0
FBN[10:0]
N. See Equation 2 for the calculation of the
baud rate using a fractional divider and
Table 82 for common baud rate values.
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