I2C Master Receive Registers
參數(shù)資料
型號: ADUC7121BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 62/96頁
文件大?。?/td> 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 9x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤
Data Sheet
ADuC7121
Rev. B | Page 65 of 96
I2C Master Receive Registers
This 8-bit MMR is the I2C master receive register.
Name:
I2C0MRX, I2C1MRX
Address:
0xFFFF0888, 0xFFFF0908
Default value: 0x00
Access:
Read only
I2C Master Transmit Registers
This 8-bit MMR is the I2C master transmit register.
Name:
I2C0MTX, I2C1MTX
Address:
0xFFFF088C, 0xFFFF090C
Default value: 0x00
Access:
Write only
I2C Master Read Count Registers
This 16-bit MMR holds the required number of bytes when the
master begins a read sequence from a slave device.
Name:
I2C0MCNT0, I2C1MCNT0
Address:
0xFFFF0890, 0xFFFF0910
Default value: 0x0000
Access:
Read and write
Table 91. I2CxMCNT0 MMR Bit Descriptions
Bit
Name
Description
15:9
Reserved.
8
I2CRECNT
Set this bit if greater than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or less.
7:0
I2CRCNT
These 8 bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required, set
these bits to 0.
I2C Master Current Read Count Registers
This 8-bit MMR holds the number of bytes received so far
during a read sequence with a slave device.
Name:
I2C0MCNT1, I2C1MCNT1
Address:
0xFFFF0894, 0xFFFF0914
Default value: 0x00
Access:
Read only
I2C Address 0 Registers
This 8-bit MMR holds the 7-bit slave address + the read/write
bit when the master begins communicating with a slave.
Name:
I2C0ADR0, I2C1ADR0
Address:
0xFFFF0898, 0xFFFF0918
Default value: 0x00
Access:
Read and write
Table 92. I2CxADR0 MMR in 7-Bit Address Mode
Bit
Name
Description
7:1
I2CADR
These bits contain the 7-bit address of the
required slave device.
0
R/W
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
Table 93. I2CxADR0 MMR in 10-Bit Address Mode
Bit
Name
Description
7:3
These bits must be set to [11110b] in 10-bit
address mode.
2:1
I2CMADR
These bits contain ADDR[9:8] in 10-bit
addressing mode.
0
R/W
Read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
I2C Address 1 Register
This 8-bit MMR is used in 10-bit addressing mode only. This
register contains the least significant byte of the address.
Name:
I2C0ADR1, I2C1ADR1
Address:
0xFFFF089C, 0xFFFF091C
Default value: 0x00
Access:
Read and write
Table 94. I2CxADR1 MMR in 10-Bit Address Mode
Bit
Name
Description
7:0
I2CLADR
These bits contain ADDR[7:0] in 10-bit
addressing mode.
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