參數(shù)資料
型號: ADUC7121BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 66/96頁
文件大?。?/td> 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤
Data Sheet
ADuC7121
Rev. B | Page 69 of 96
Bit
Name
Description
4
I2CSRxFO
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
3
I2CSRXQ
I2C slave receive request bit.
This bit is set to 1 when the Rx FIFO of the slave is not empty. This bit causes an interrupt to occur if the I2CSRXENI
bit in I2CxSCTL is set.
The Rx FIFO must be read or flushed to clear this bit.
2
I2CSTXQ
I2C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the read bit
transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCTL is set.
This bit is cleared in all other conditions.
1
I2CSTFE
I2C slave FIFO underflow status bit.
This bit is high if the Tx FIFO is empty when a master requests data from the slave. This bit asserts at the rising edge
of SCL during the read bit.
This bit clears in all other conditions.
0
I2CETSTA
I2C slave early transmit FIFO status bit.
If the I2CSETEN bit in I2CxSCTL is = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCTL is = 1, this bit goes high just after the positive edge of SCL during the write bit
transmission. This bit asserts once only for a transfer.
This bit is cleared after being read.
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