參數(shù)資料
型號(hào): ADUC7121BBCZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 75/96頁(yè)
文件大小: 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 126KB(63K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤(pán)
Data Sheet
ADuC7121
Rev. B | Page 77 of 96
PLACLK Register
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. The maximum frequency when using the GPIO pins as
the clock input for the PLA blocks is 41.78 MHz.
Name:
PLACLK
Address:
0xFFFF0B40
Default value: 0x00
Access:
Read and write
Table 105. PLACLK MMR Bit Descriptions
Bit
Value
Description
7
Reserved.
6:4
Block 1 clock source selection.
000
GPIO clock on P0.5 of the P0.5/CS/PLAI[10]/
ADCCONVST pin.
001
GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.
010
GPIO clock on the P0.7 of the P0.7/TRST/PLAI[3] pin.
011
HCLK (core clock).
100
OCLK (32.768 kHz external crystal).
101
Timer1 overflow.
Other
Reserved.
3
Reserved.
2:0
Block 0 clock source selection.
000
GPIO clock on P0.5. on P0.5 of the P0.5/CS/
PLAI[10]/ADCCONVST pin.
001
GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.
010
GPIO clock on P0.7 of the P0.7/TRST/PLAI[3] pin.
011
HCLK (core clock).
100
OCLK (32.768 kHz external crystal).
101
Timer1 overflow.
Other
Reserved.
PLAIRQ Register
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the normal interrupt request IRQ (IRQ).
Name:
PLAIRQ
Address:
0xFFFF0B44
Default value: 0x0000
Access:
Read and write
Table 106. PLAIRQ MMR Bit Descriptions
Bit
Value
Description
15:13
Reserved.
12
PLA IRQ1 enable bit.
Set by the user to enable IRQ1 output from
the PLA.
Cleared by the user to disable IRQ1 output
from the PLA.
Bit
Value
Description
11:8
PLA IRQ1 source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
7:5
Reserved.
4
PLA IRQ0 enable bit.
Set by the user to enable IRQ0 output from
the PLA.
Cleared by the user to disable IRQ0 output
from the PLA.
3:0
PLA IRQ0 source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
PLAADC Register
PLAADC is the PLA source for the ADC start conversion signal.
Name:
PLAADC
Address:
0xFFFF0B48
Default value: 0x00000000
Access:
Read and write
Table 107. PLAADC MMR Bit Descriptions
Bit
Value
Description
31:5
Reserved.
4
ADC start conversion enable bit.
Set by the user to enable an ADC start
conversion from the PLA.
Cleared by the user to disable an ADC start
conversion from the PLA.
3:0
ADC start conversion source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
PLADIN Register
PLADIN is a data input MMR for PLA.
Name:
PLADIN
Address:
0xFFFF0B4C
Default value: 0x00000000
Access:
Read and write
Table 108. PLADIN MMR Bit Descriptions
Bit
Description
31:16
Reserved.
15:0
Input bit from Element 15 to Element 0.
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