
Data Sheet
ADuC7121
Rev. B | Page 5 of 96
SPECIFICATIONS
AVDD = IOVDD = 3.0 V to 3.6 V, PVDD = 2.0 V ± 5%, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = 10°C to +95°C, unless
otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
Eight acquisition clocks and fADC/2
ADC Power-Up Time
5
μs
Resolution
12
Bits
Integral Nonlinearity
±0.6
±2
LSB
2.5 V internal reference, not production tested
for PADC0 and PADC1 channels
Differential Nonlinearit
y3, 4±0.5
+1.4/0.99
LSB
2.5 V internal reference, guaranteed
monotonic
DC Code Distribution
1
LSB
ADC input is a dc voltage
Internally unbuffered channels
Offset Error
All Channels Except IDACx
Channels
±2
±5
LSB
IDACx Channels Only
1
% of full
scale
Offset Error Match
±1
LSB
Gain Error
±2
±5
LSB
Gain Error Match
±1
LSB
DYNAMIC PERFORMANCE
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS,
internally unbuffered channels
Signal-to-Noise Ratio (SNR)
69
dB
Includes distortion and noise components
Total Harmonic Distortion (THD)
78
dB
Peak Harmonic or Spurious Noise
75
dB
Channel-to-Channel Crosstalk
80
dB
Measured on adjacent channels
ANALOG INPUT
Input Voltage Ranges
Differential Mode
V
Single-Ended Mode
0 to VREF
V
Buffer bypassed
0.15
AVDD 1.5
V
Buffer enabled
Leakage Current
±0.2
±1
A
Input Capacitance
20
pF
During ADC acquisition buffer bypassed
20
pF
During ADC acquisition buffer enabled
PADC0x INPUT
28.3 kΩ resistor, PGA gain = 3, acquisition
time = 3.2 μs, pseudo differential mode
Full-Scale Input Range
20
1000
A
0.15
2
nA
Resolution
11
Bits
0.1% accuracy, 5 ppm external resistor for
current to voltage
1
%
50
ppm/°C
3
6
nA
PGA offset not included
30
60
pA/°C
PADC0x Compliant Range
0.1
AVDD 1.2
V