參數(shù)資料
型號(hào)： ADUC7121BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/96頁(yè)
文件大?。?/td> 0K
描述： IC ARM7TDMI MCU 126KB 108CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 托盤
Data Sheet
ADuC7121
Rev. B | Page 27 of 96
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from a 3.0 V to 3.6 V
supply and is capable of providing a throughput of up to 1 MSPS
when the clock source is 41.78 MHz. This block provides the
user with a multichannel multiplexer, a differential track-and-
hold, an on-chip reference, and an ADC.
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of the
following three modes:
Fully differential mode, for small and balanced signals.
Single-ended mode, for any single-ended signals.
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input.
The converter accepts an analog input range of 0 V to VREF
when operating in single-ended mode or pseudo differential
mode. In fully differential mode, the input signal must be balanced
around a common-mode voltage (VCM) in the range of 0 V to
AVDD and with a maximum amplitude of 2 VREF (see Figure 12).
Figure 12. Examples of Balanced Signals for Fully Differential Mode
A high precision, low drift, and factory calibrated 2.5 V reference
is provided on chip. An external reference can also be connected
as described in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external ADC
CONVST pin, an output generated from
the on-chip PLA, a Timer0, or a Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
If the signal has not been deasserted by the time the ADC
conversion is complete, a second conversion begins automatically.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively creating an additional
ADC channel input. This facilitates an internal temperature sensor
channel, measuring die temperature to an accuracy of ±3°C.
The ADuC7121 is modified in a way that differentiates its ADC
structure from other devices in the ADuC702x family.
The PADC0x and PADC1x inputs connect to a PGA and allow for
a gain from 1 to 5 with 32 steps. The remaining channels can be
configured as single ended or differential. A buffer is provided
before the ADC for measuring internal channels.
ADC TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
For both pseudo differential and single-ended modes, the input
range is 0 to VREF. In addition, the output coding is straight binary
in both pseudo differential and single-ended modes with
1 LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 μV
when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 13.
Figure 13. ADC Transfer Function in Pseudo Differential Mode or
Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN inputs (that is, VIN+
VIN). Therefore, the maximum amplitude of the differential
signal is VREF to +VREF p-p (2 × VREF). This is regardless of the
common mode (CM). The common mode is the average of the
two signals (VIN+ + VIN)/2, and is, therefore, the voltage that the
two inputs are centered on, which results in the span of each
input being CM ± VREF/2. This voltage must be set up externally,
and its range varies with VREF (see the Driving the Analog
Inputs section).
The output coding is twos complement in fully differential
mode with
1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V
The output result is ±11 bits, but this is shifted by one bit to the
right. This allows the result in ADCDAT to be declared as a
signed integer when writing C code. The designed code transi-
tions occur midway between successive integer LSB values (that is,
AVDD
VCM
0
2VREF
0
94
92
-01
2
O
UT
P
UT
CO
DE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB
0V
+FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB =
FS
4096
09
49
2-
0
13
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