參數(shù)資料
型號: ADSP-TS203SABPZ050
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述: 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝: 25 X 25 MM, MS-034, BGA-576
文件頁數(shù): 45/48頁
文件大?。?/td> 2017K
代理商: ADSP-TS203SABPZ050
Rev. C
|
Page 6 of 48
|
December 2006
ADSP-TS203S
EXTERNAL PORT (OFF-CHIP
MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS203S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 32-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 500M bytes per
second over the external bus.
The external bus is configured for 32-bit, little-endian opera-
tions. Unlike the ADSP-TS201, the ADSP-TS203S processor’s
external port cannot support 64-bit operations; the external bus
width control bits (Bits 21-19) must = 0 in the SYSCON regis-
ter—all other values are illegal for the ADSP-TS203S processor.
Because the external port is restricted to 32 bits on the ADSP-
TS203S processor, there are a number of pinout differences
between the ADSP-TS203S processor and the ADSP-TS201
processor.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS203S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Figure 3. ADSP-TS203S Memory Map
RESERVED
INTE RNAL REGISTERS (UREGS )
I NTERNAL MEMORY BLOCK 4
INTERNAL MEMORY BLO CK 2
INTERNAL MEMORY BLO CK 0
0x03FFFFFF
0x001E0000
0x001E03FF
0x000C7FFF
0x000C0000
0x00087FFF
0x00080000
0x00047FFF
0x00040000
0x00007FFF
0x00000000
INTERNAL SPACE
PROCESSO R ID 7
PROCESSO R ID 6
PROCESSO R ID 5
PROCESSO R ID 4
PROCESSO R ID 3
PROCESSO R ID 2
PROCESSO R ID 1
PROCESSO R ID 0
BROADCAST
HOST (
MSH)
BANK 1 (
MS1)
BANK 0 (
MS0)
MSSD BANK 0 (
MSSD0)
INTERNAL MEMORY
0x50000000
0x40000000
0x38000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x1C000000
0x18000000
0x14000000
0x10000000
0x0C000000
0x03FFFFFF
0x00000000
GLOBAL SPACE
0xFFFFFFFF
M
U
L
T
IP
R
O
C
E
S
O
R
M
E
M
O
R
Y
S
P
A
C
E
X
T
E
R
N
A
L
M
E
M
O
R
Y
S
P
A
C
E
EACH IS A COPY
OF INTERNAL SPACE
RESERVED
I NTERNAL MEMORY BLOCK 6
RESERVED
SOC REGI STERS (UREGS)
0x001F0000
0x001F03FF
MSSD BANK 1 (
MSSD1)
MSSD BANK 2 (
MSSD2)
MSSD BANK 3 (
MSSD3)
0x60000000
0x70000000
0x80000000
RESERVED
0x54000000
0x44000000
0x64000000
0x74000000
RESERVED
RESE RVED
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