參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
ADSP-TS203S
Rev. C
|
Page 23 of 48
|
December 2006
TIMING SPECIFICATIONS
With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all ac timing for the ADSP-TS203S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the
ADSP-TS203S processor has few calculated (formula-based)
values. For information on ac timing, see General AC Timing.
For information on link port transfer timing, see Link Port Low
General AC Timing
Timing is measured on signals when they cross the 1.25 V level
as described in Figure 15 on Page 28. All delays (in nanosec-
onds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
The general ac timing data appears in Table 22 and Table 29. All
ac specifications are measured with the load specified in
Figure 36 on Page 37, and with the output drive strength set to
strength 4. In order to calculate the output valid and hold times
for different load conditions and/or output drive strengths, refer
Fall Time vs. Load Capacitance) and Figure 45 on Page 38 (Out-
put Valid vs. Load Capacitance and Drive Strength).
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
FLAG3–0, and TMR0E pins appears in Table 21.
Table 21. AC Asynchronous Signal Specifications
Name
Description
Pulse Width Low (Min)
Pulse Width High (Min)
IRQ3–0
1
Interrupt Request
2
× tSCLK ns
2
× tSCLK ns
DMAR3–01
DMA Request
2
× tSCLK ns
2
× tSCLK ns
FLAG3–02
FLAG3–0 Input
2
× tSCLK ns
2
× tSCLK ns
TMR0E3
Timer 0 Expired
4
× tSCLK ns
1 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
2 For output specifications on FLAG3–0 pins, see Table 29.
3 This pin is a strap option. During reset, an internal resistor pulls the pin low.
Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time
Parameter
Description
Grade = 050 (500 MHz)
Unit
Min
Max
tCCLK
1
Core Clock Cycle Time
2.0
12.5
ns
1 CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t
SCLK) divided by the system clock ratio
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 45.
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
CCLK
tCCLK
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