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參數(shù)資料
| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind |
| 中文描述： | 32-BIT, 125 MHz, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, BGA-576 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 2017K |
| 代理商： | ADSP-TS203SABPZ050 |
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Rev. C
|
Page 30 of 48
|
December 2006
ADSP-TS203S
Link Port—Data Out Timing
Figure 22, and Figure 23 provide the data out timing for the
LVDS link ports.
Table 32. Link Port—Data Out Timing
Parameter
Description
Min
Max
Unit
Outputs
tREO
Rising Edge (Figure 19)350
ps
tFEO
Falling Edge (Figure 19)350
ps
tLCLKOP
LxCLKOUT Period (Figure 18)
Greater of 4.0 or
0.9
× LCR × tCCLK1, 2, 3
Smaller of 12.5 or
1.1
× LCR × tCCLK1, 2, 3
ns
tLCLKOH
LxCLKOUT High (Figure 18)0.4
× tLCLKOP1
0.6
× tLCLKOP1
ns
tLCLKOL
LxCLKOUT Low (Figure 18)0.4
× tLCLKOP1
0.6
× tLCLKOP1
ns
tCOJT
LxCLKOUT Jitter (Figure 18)
±1504, 5, 6
±2507
ps
tLDOS
LxDATO Output Setup (Figure 20)0.25
× LCR × tCCLK –0.10 × tCCLK1, 4, 8
0.25
× LCR × tCCLK –0.15 × tCCLK1, 5, 6, 8
0.25
× LCR × tCCLK –0.30 × tCCLK 1, 7, 8
ns
tLDOH
LxDATO Output Hold (Figure 20)0.25
× LCR × tCCLK –0.10 × tCCLK1, 4, 8
0.25
× LCR × tCCLK –0.15 × tCCLK1, 5, 6, 8
0.25
× LCR × tCCLK –0.30 × tCCLK 1, 7, 8
ns
tLACKID
Delay from LxACKI rising edge to first trans-
mission clock edge (Figure 21)
16
× LCR × tCCLK1, 2
ns
tBCMPOV
LxBCMPO Valid (Figure 21)2
× LCR × tCCLK1, 2
ns
tBCMPOH
LxBCMPO Hold (Figure 22)3
× TSW – 0.51, 9
ns
Inputs
tLACKIS
LxACKI low setup to guarantee that the trans-
mitter stops transmitting (Figure 22)
LxACKI high setup to guarantee that the trans-
mitter continues its transmission without any
interruption (Figure 23)16
× LCR × tCCLK1, 2
ns
tLACKIH
LxACKI High Hold Time (Figure 23)0.51
ns
1 Timing is relative to the 0 differential voltage (V
OD = 0).
2 LCR (link port clock ratio) = 1, 1.5, 2, or 4. tCCLK is the core period.
3 For the cases of tLCLKOP = 4.0 ns and tLCLKOP = 12.5 ns, the effect of tCOJT specification on output period must be considered.
4 LCR= 1.
5 LCR= 1.5.
6 LCR= 2.
7 LCR= 4.
8 The tLDOS and tLDOH values include LCLKOUT jitter.
9 TSW is a short-word transmission period. For a 4-bit link, it is 2
× LCR × tCCLK. For a 1-bit link, it is 8 × LCR × tCCLK ns.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410S | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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