參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁(yè)數(shù)： 1/48頁(yè)
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
a
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
TigerSHARC
Embedded Processor
ADSP-TS203S
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.326.3113
2006 Analog Devices, Inc. All rights reserved.
KEY FEATURES
500 MHz, 2.0 ns instruction cycle rate
4M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid array
package
Dual-computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual-integer ALUs, providing data addressing and pointer
manipulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
Integrated I/O includes 10-channel DMA controller, external
port, two link ports, SDRAM controller, programmable flag
pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for large, demanding
multiprocessor DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in Table 1)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other (multiprocessor)
DSPs
Eases programming through extremely flexible instruction
set and high-level-language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Figure 1. Functional Block Diagram
T
L0
4
8
4
8
4
8
4
8
4
IN
OUT
HOST
MULTI-
PROC
C-BUS
ARB
DATA
32
LINK PORTS
JTAG PORT
EXTERNAL
PORT
ADDR
32
6
SOC BUS
DMA
JTAG
SDRAM
CTRL
EXT DMA
REQ
J-BUS DATA
IAB
PC
BTB
ADDR
FETCH
PROGRAM
SEQUENCER
COMPUTATIONAL BLOCKS
J-BUS ADDR
K-BUS DATA
K-BUS ADDR
I-BUS DATA
I-BUS ADDR
S-BUS DATA
S-BUS ADDR
INTEGER
KALU
INTEGER
JALU
32
32-BIT × 32-BIT
DATA ADDRESS GENERATION
X
REGISTER
FILE
32-BIT × 32-BIT
MUL
ALU
SHIFT
DAB
128
DAB
128
MEMORY BLOCKS
A
D
4M BITS INTERNAL MEMORY
4 × CROSSBAR CONNECT
(PAGE CACHE)
A
D
A
D
A
D
SOC
I/F
Y
REGISTER
FILE
32-BIT × 32-BIT
MUL
ALU
SHIFT
L1
IN
OUT
CTRL
8
CTRL
10
32
128
32
128
32
128
21
128
4
32-BIT × 32-BIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
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