參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁數(shù)： 18/48頁
文件大小： 2017K
代理商： ADSP-TS203SABPZ050
ADSP-TS203S
Rev. C
|
Page 25 of 48
|
December 2006
Table 25. Power-Up Timing1
Parameter
Min
Max
Unit
Timing Requirement
tVDD_DRAM
VDD_DRAM Stable After VDD, VDD_A, VDD_IO Stable
>0
ms
1 For information about power supply sequencing and monitoring solutions, please visit www.analog.com/sequencing.
Figure 12. Power-Up Timing
Table 26. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tRST_IN_PWR
RST_IN Deasserted After VDD, VDD_A, VDD_IO, VDD_DRAM, SCLK, and Static/
Strap Pins Stable
2
ms
tTRST_IN_PWR
1
TRST Asserted During Power-Up Reset
100
× tSCLK
ns
Switching Characteristic
tRST_OUT_PWR
RST_OUT Deasserted After RST_IN Deasserted
1.5
ms
1 Applies after VDD, VDD_A, VDD_IO, VDD_DRAM, and SCLK are stable and before RST_IN deasserted.
Figure 13. Power-Up Reset Timing
VDD
VDD_A
VDD_IO
VDD_DRAM
tVDD_DRAM
RST_OUT
tRST_OUT_PWR
TRST
tTRST_IN_PWR
SCLK, VDD, VDD_A,
VDD_IO, VDD_DRAM
STATIC/STRAP PINS
RST_IN
tRST_IN_PWR
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