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參數(shù)資料
| 型號： | ADSP-TS203SABPZ050 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind |
| 中文描述： | 32-BIT, 125 MHz, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, BGA-576 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 2017K |
| 代理商： | ADSP-TS203SABPZ050 |
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ADSP-TS203S
Rev. C
|
Page 3 of 48
|
December 2006
GENERAL DESCRIPTION
The ADSP-TS203S TigerSHARC processor is an ultrahigh per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting floating-point (IEEE 32-bit and extended
precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) pro-
cessing—to set a new standard of performance for digital signal
processors. The TigerSHARC static superscalar architecture lets
the DSP execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Four independent 128-bit wide internal data buses, each con-
necting to the four 1M bit memory banks, enable quad-word
data, instruction, and I/O access and provide 28G bytes per sec-
ond of internal memory bandwidth. Operating at 500 MHz, the
ADSP-TS203S processor’s core has a 2.0 ns instruction cycle
time. Using its single-instruction, multiple-data (SIMD) fea-
tures, the ADSP-TS203S processor can perform four billion,
40-bit MACS or one billion, 80-bit MACS per second. Table 1
shows the DSP’s performance benchmarks.
The ADSP-TS203S processor is code compatible with the other
TigerSHARC processors.
The Functional Block Diagram on Page 1 shows the
ADSP-TS203S processor’s architectural blocks. These blocks
include
Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status register
A program sequencer with instruction alignment buffer
(IAB) and branch target buffer (BTB)
An interrupt controller that supports hardware and soft-
ware interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
Four 128-bit internal data buses, each connecting to the
four 1M-bit memory banks
On-chip DRAM (4M-bit)
An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
A 10-channel DMA controller
Two full-duplex LVDS link ports
Two 64-bit interval timers and timer expired pin
An 1149.1 IEEE-compliant JTAG test access port for on-
chip emulation
Figure 2 shows a typical single-processor system with external
SRAM and SDRAM. Figure 4 on Page 8 shows a typical multi-
processor system.
Table 1. General-Purpose Algorithm Benchmarks
at 500 MHz
Benchmark
Speed
Clock
Cycles
32-bit algorithm, 1 billion MACS/s peak performance
1K point complex FFT
1 (Radix2)
1 Cache preloaded.
18.8 μs
9419
64K point complex FFT
1 (Radix2)
2.8 ms
1397544
FIR filter (per real tap)
1 ns
0.5
[8
× 8][8 × 8] matrix multiply (complex,
floating-point)
2.8 μs
1399
16-bit algorithm, 4 billion MACS/s peak performance
256 point complex FFT1 (Radix 2)
1.9 μs
928
I/O DMA transfer rate
External port
500M bytes/s n/a
Link ports (each)
500M bytes/s n/a
Figure 2. ADSP-TS203S Single-Processor System with External SDRAM
BOFF
CONTROLIMP1–0
DMAR3–0
HBG
HBR
DMA DEVICE
(OPTIONAL)
DATA
MSH
FLAG3–0
ID2–0
IOEN
RAS
CAS
LDQM
SDWE
SDCKE
SDA10
IRQ3–0
SCLK
SCLKRAT2–0
SCLK_VREF
VREF
TMR0E
BM
MSSD3–0
BUSLOCK
SDRAM
MEMORY
(OPTIONAL)
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
POR_IN
JTAG
ADSP-TS203S
BMS
CLOCK
LINK
DEVICES
(2 MAX)
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY
(OPTIONAL)
OE
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
BR7–0
CPA
MS1–0
DATA31–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
BRST
REFERENCE
RD
WRL
DPA
DS2–0
CS
LxCLKINP/N
LxACKO
LxDATI3–0P/N
LxBCMPI
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
IORD
IOWR
RST_OUT
RST_IN
REFERENCE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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