參數(shù)資料
型號： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁數(shù)： 20/48頁
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
ADSP-TS203S
Rev. C
|
Page 27 of 48
|
December 2006
Table 29. AC Signal Specifications
(All values in this table are in nanoseconds.)
Name
Description
In
put
S
e
tu
p
(M
in
)
In
put
Hold
(M
in
)
Ou
tp
u
tV
a
li
d
(M
a
x
)
Ou
tp
u
tH
o
ld
(M
in
)
Ou
tp
u
tEn
ab
le
(M
in
)1
Ou
tpu
tDi
sab
le
(M
a
x
)1
Re
fe
re
nce
Cl
ock
ADDR31–0
External Address Bus
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
DATA31–0
External Data Bus
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
MSH
Memory Select HOST Line
—
4.0
1.0
1.15
2.0
SCLK
MSSD3–0
Memory Select SDRAM Lines
1.5
0.5
4.0
1.0
2.0
SCLK
MS1–0
Memory Select for Static Blocks
—
4.0
1.0
1.15
2.0
SCLK
RD
Memory Read
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
WRL
Write Low Word
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
ACK
Acknowledge for Data High to Low
1.5
0.5
3.6
1.0
1.15
2.0
SCLK
Acknowledge for Data Low to High
1.5
0.5
4.2
0.9
1.15
2.0
SCLK
SDCKE
SDRAM Clock Enable
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
RAS
Row Address Select
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
CAS
Column Address Select
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
SDWE
SDRAM Write Enable
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
LDQM
Low Word SDRAM Data Mask
—
4.0
1.0
1.15
2.0
SCLK
SDA10
SDRAM ADDR10
—
4.0
1.0
1.15
2.0
SCLK
HBR
Host Bus Request
1.5
0.5
—
SCLK
HBG
Host Bus Grant
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
BOFF
Back Off Request
1.5
0.5
—
——
—SCLK
BUSLOCK
Bus Lock
—
4.0
1.0
1.15
2.0
SCLK
BRST
Burst Pin
1.5
0.5
4.0
1.0
1.15
2.0
SCLK
BR7–0
Multiprocessing Bus Request Pins
1.5
0.5
4.0
1.0
—
SCLK
BM
Bus Master Debug Aid Only
—
4.0
1.0
—
SCLK
IORD
I/O Read Pin
—
4.0
1.0
2.0
SCLK
IOWR
I/O Write Pin
—
4.0
1.0
1.15
2.0
SCLK
IOEN
I/O Enable Pin
—
4.0
1.0
1.15
2.0
SCLK
CPA
Core Priority Access High to Low
1.5
0.5
4.0
1.0
0.75
2.0
SCLK
Core Priority Access Low to High
1.5
0.5
29.5
2.0
0.75
2.0
SCLK
DPA
DMA Priority Access High to Low
1.5
0.5
4.0
1.0
0.75
2.0
SCLK
DMA Priority Access Low to High
1.5
0.5
29.5
2.0
0.75
2.0
SCLK
BMS
Boot Memory Select
—
4.0
1.0
1.15
2.0
SCLK
FLAG3–02
FLAG Pins
—
4.0
1.0
1.15
2.0
SCLK
RST_IN 3, 4
Global Reset Pin
1.5
2.5
—
SCLK5
TMS
Test Mode Select (JTAG)
1.5
0.5
—
TCK
TDI
Test Data Input (JTAG)
1.5
0.5
—
TCK
TDO
Test Data Output (JTAG)
—
4.0
1.0
0.75
2.0
TCK
6
TRST
Test Reset (JTAG)
1.5
0.5
—
TCK
EMU
7
Emulation High to Low
—
5.5
2.0
1.15
4.0
TCK or SCLK
ID2–08
Static Pins—Must Be Constant
—
CONTROLIMP1–08
Static Pins—Must Be Constant
—
DS2–08
Static Pins—Must Be Constant
—
SCLKRAT2–0
8
Static Pins—Must Be Constant
—
相關PDF資料
PDF描述
ADSQ-1410-EX-C 4-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA66
ADT-2734-MM-35M-02 MALE-MALE, RF STRAIGHT ADAPTER, PLUG
ADT-2744-MM-HNO-02 MALE-MALE, RF STRAIGHT ADAPTER, PLUG
ADT-2779-TF-SMF-00 PANEL MOUNT, FEMALE, RF STRAIGHT ADAPTER
ADT-2802-7M-HNF-02 MALE-FEMALE, RF STRAIGHT ADAPTER, JACK
相關代理商/技術參數(shù)
參數(shù)描述
ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
ADSQ-1410 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410-EX-C 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter
ADSQ-1410S 功能描述:模數(shù)轉換器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*