參數(shù)資料
型號(hào)： ADS6224IRGZ25
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, VQFN-48
文件頁(yè)數(shù)： 73/73頁(yè)
文件大小： 3182K
代理商： ADS6224IRGZ25
www.ti.com
TIMING SPECIFICATIONS
(1)
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
Typical values are at 25
°C, min and max values are across the full temperature range T
MIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF
(2), I
O = 3.5 mA,
RL = 100
(3), no internal termination, unless otherwise noted.
ADS6225
ADS6224
ADS6223
ADS6222
TEST
PARAMETER
UNIT
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tJ
Aperture jitter Uncertainty in the
250
fs rms
sampling instant
Interface: 2-wire, DDR bit clock, 14x serialization
From data
Data setup
tsu
cross-over to bit
0.35
0.55
0.45
0.65
0.85
0.8
1.1
ns
time(4) (5)(6)
clock cross-over
From bit clock
Data hold
th
cross-over to data
0.35
0.58
0.5
0.7
0.9
0.8
1.1
ns
time(4) (5)(6)
cross-over
Input clock rising
Clock
edge cross-over to
tpd_clk
propagation
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
3.4
4.4
5.4
ns
frame clock rising
delay (6)
edge cross-over
Bit clock
cycle-cycle
350
ps pp
jitter (5)
Frame clock
cycle-cycle
75
ps pp
jitter (5)
Below specifications apply for 5 MSPS
≤ Sampling freq ≤ 125 MSPS and all interface options
Delay from input
Aperture
clock rising edge to
tA
1
2
3
1
2
3
1
2
3
1
2
3
ns
delay
the actual sampling
instant
Aperture
Channel-channel
delay
within same device
–250
±80
250
–250
±80
250
–250
±80
250
–250
±80
250
ps
variation
Time for a sample
ADC Latency
to propagate to
Clock
12
(7)
ADC outputs, see
cycles
Time to valid data
after coming out of
100
μs
global power down
Time to valid data
Wake up time after input clock is
100
μs
re-started
Time to valid data
clock
after coming out of
200
cycles
channel standby
Data rise
From –100 mV to
ps
tRISE
50
100
200
50
100
200
50
100
200
50
100
200
time
+100 mV
From +100 mV to
tFALL
Data fall time
50
100
200
50
100
200
50
100
200
50
100
200
ps
–100 mV
Bit clock and
From –100 mV to
tRISE
Frame clock
50
100
200
50
100
200
50
100
200
50
100
200
ps
+100 mV
rise time
(1)
Timing parameters are ensured by design and characterization and not tested in production.
(2)
CL is the External single-ended load capacitance between each output pin and ground.
(3)
Io Refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
(4)
Timing parameters are measured at the end of a 2 inch pcb trace (100-
Ω characteristic impedance) terminated by RLand CL.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6)
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
(7)
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
listed in Table 28.
Copyright 2007, Texas Instruments Incorporated
9
Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222
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ADS6224IRGZT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12b 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6224IRGZTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12B 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6225 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
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