參數(shù)資料
型號: ADS6224IRGZ25
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X 7 MM, GREEN, PLASTIC, VQFN-48
文件頁數(shù): 7/73頁
文件大小: 3182K
代理商: ADS6224IRGZ25
www.ti.com
SERIAL INTERFACE
Register Reset
T0109-03
t
(SCLK)
t
(DSU)
t
(DH)
t
(SLOADS)
D7
A4
D3
A0
D5
A2
D1
D9
D6
A3
D2
D10
D4
A1
D0
D8
SDATA
SCLK
SEN
RESET
t
(SLOADH)
Register Address
RegisterData
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with
non-50% duty cycle SCLK.
The first 5 bits of the 16-bit word are the address of the register while the next 11 bits are the register data.
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
Figure 4. Serial Interface Timing
Copyright 2007, Texas Instruments Incorporated
15
Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222
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