參數(shù)資料
型號(hào)： ADS6224IRGZ25
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, VQFN-48
文件頁數(shù)： 46/73頁
文件大小： 3182K
代理商： ADS6224IRGZ25
www.ti.com
CLOCK BUFFER GAIN
POWER DOWN MODES
Global Power Down
Channel Standby
Input Clock Stop
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than 1 Vpp to
avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (Table 15) and increases
monotonically from Gain 0 to Gain 4 settings. Table 23 shows the minimum clock amplitude supported for each
gain setting.
Table 23. Minimum Clock Amplitude across gains
CLOCK BUFFER GAIN
MINIMUM CLOCK AMPLITUDE SUPPORTED, mVpp differential
Gain 0 (minimum gain)
800
Gain 1 (default gain)
400
Gain 2
300
Gain 3
200
Gain 4 (highest gain)
150
The ADS622X has three power down modes – global power down, channel standby, and input clock stop.
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (Table 14). The
output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100
μs.
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (Table 14). The output
LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
The converter enters this mode:
If the input clock frequency falls below 1 MSPS or
If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100
μs.
50
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222
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ADS6224IRGZRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12B 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6224IRGZT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12b 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6224IRGZTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12B 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6225 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
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