參數(shù)資料
型號: ADS6224IRGZ25
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X 7 MM, GREEN, PLASTIC, VQFN-48
文件頁數(shù): 6/73頁
文件大?。?/td> 3182K
代理商: ADS6224IRGZ25
www.ti.com
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
Independent of the programming mode used, after power-up the parallel pins PDNA,PDNB,CFG1 to CFG4 will
automatically configure the device as per the voltage applied (Table 7 to Table 12).
Table 7. PDNA Control Pin
PDNA
DESCRIPTION
0
Normal operation
AVDD
Channel A ADC power down global
Table 8. PDNB Control Pin
PDNB
DESCRIPTION
0
Normal operation
AVDD
Channel B ADC power down global
Table 9. CFG1 Control Pin
CFG1
DESCRIPTION
0
DDR Bit clock and 1-wire interface
(3/8)LVDD
Not used
(5/8)LVDD
SDR Bit clock and 2-wire interface
LVDD
DDR Bit clock and 2-wire interface
Table 10. CFG2 Control Pin
CFG2
DESCRIPTION
0
12x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock
mode)
(3/8)LVDD
14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock
mode)
(5/8)LVDD
14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
LVDD
12x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
Table 11. CFG3 Control Pin
CFG3
RESERVED – TIE TO GROUND
Table 12. CFG4 Control Pin
CFG4
DESCRIPTION
0
MSB First and 2s complement
(3/8)LVDD
MSB First and offset binary
(5/8)LVDD
LSB First and offset binary
LVDD
LSB First and 2s complement
14
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222
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