參數(shù)資料
型號(hào)： ADS6224IRGZ25
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, GREEN, PLASTIC, VQFN-48
文件頁(yè)數(shù)： 57/73頁(yè)
文件大?。?/td> 3182K
代理商： ADS6224IRGZ25
www.ti.com
CAPTURE TEST PATTERNS
SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007
ADS622X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended
to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures
sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 6 '1's followed by 6 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data till it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS622X includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Table 26. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern – <D11-D0> alternates between 101010101010 and 010101010101 every clock cycle.
Outputs a 12-bit custom pattern. The 12-bit custom pattern can be specified into two serial interface registers. In the 2-wire
Custom
interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync
Outputs a sync pattern.
Deskew
Outputs deskew pattern. Either <D11–D0> = 101010101010 OR <D11–D0> = 010101010101 every clock cycle.
Table 27. SYNC Pattern
INTERFACE OPTION
SERIALIZATION
SYNC PATTERN ON EACH WIRE
12x
MSB-111111000000-LSB
1-Wire
14x
MSB-11111110000000-LSB
12x
MSB-111000-LSB
2-Wire
14x
MSB-1111000-LSB
60
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222
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ADS6224IRGZTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 12B 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS6225 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
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