
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E| Page 88 of 96
Bit
Location
Bit Mnemonic
Default Value
Description
12
CF1LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
13
CF2LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
14
CF3LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
15
Reserved
0
Reserved. This bit does not manage any functionality.
Table 46. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
Location
Bit Mnemonic
Default Value
Description
If current channel compensation is necessary, these bits can vary only between 0 and 383.
If voltage channel compensation is necessary, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
9:0
PHCALVAL
0000000000
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
15:10
Reserved
000000
Reserved. These bits do not manage any functionality.
Table 47. PHSIGN Register (Address 0xE617)
Bit
Location
Bit Mnemonic
Default Value
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
0
AWSIGN
0
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
1
BWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
2
CWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
3
SUM1SIGN
0
0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
4
AVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
5
BVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
6
CVARSIGN
0
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive. This bit is always 0 for ADE7854.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is negative.
7
SUM2SIGN
0
0: if the sum of all phase powers in the CF2 datapath is positive.
1: if the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2
datapath are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.