參數(shù)資料
型號(hào): ADE7878ACPZ
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述: SPECIALTY ANALOG CIRCUIT, QCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁數(shù): 69/96頁
文件大?。?/td> 1096K
代理商: ADE7878ACPZ
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 71 of 96
Figure 88 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.
Figure 89 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
See Table 53 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 24 lists the time it takes to execute an HSDC data transfer
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
Table 24. Communication Times for Various HSDC Settings
HXFER[1:0]
HGAP
HSIZE1
HCLK
Communication Time (μs)
00
0
N/A
0
64
00
0
N/A
1
128
00
1
0
77.125
00
1
0
1
154.25
00
1
0
119.25
00
1
238.25
01
0
N/A
0
28
01
0
N/A
1
56
01
1
0
33.25
01
1
0
1
66.5
01
1
0
51.625
01
1
103.25
10
0
N/A
0
36
10
0
N/A
1
72
10
1
0
43
10
1
0
1
86
10
1
0
66.625
10
1
133.25
1 N/A means not applicable.
HSCLK
HSD
HSA
0
31
0
31
0
31
0
31
IAVW (32 BITS)
VAWV (32 BITS)
IBWV (32 BITS)
CVAR (32 BITS)
08
51
0-
0
66
Figure 87. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
HSCLK
HSDATA
HSACTIVE
0
31
0
31
0
31
IAVW (32 BITS)
7 HCLK CYCLES
VAWV (32 BITS)
IBWV (32 BITS)
7 HCLK CYCLES
0
31
CVAR (32 BITS)
08
51
0-
06
7
Figure 88. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
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