參數(shù)資料
型號(hào)： ADE7878ACPZ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind
中文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40
文件頁(yè)數(shù)： 79/96頁(yè)
文件大小： 1096K
代理商： ADE7878ACPZ
ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 80 of 96
Address
Register
Name
Description
0xE707
Version
R
8
U
Version of die.
0xEBFF
Reserved
8
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port. See the
section for details.
0xEC00
LPOILVL
R/W
8
U
0x07
Overcurrent threshold used during
PSM2 mode (ADE7868 and ADE7878
only). See Table 54 in which the register
is detailed.
0xEC01
CONFIG2
R/W
8
U
0x00
Configuration register used during
PSM1 mode. See Table 55.
1 R is read, and W is write.
2 32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3 U is unsigned register, and S is signed register in twos complement format.
4 N/A is not applicable.
Table 34. HPFDIS Register (Address 0x43B6)
Bit
Location
Default
Value
Description
23:0
00000000
When HPFDIS = 0x00000000, then all high-pass filters in voltage and current channels are enabled. When the
register is set to any nonzero value, all high-pass filters are disabled.
Table 35. IPEAK Register (Address 0xE500)
Bit Location
Bit Mnemonic
Default Value
Description
23:0
IPEAKVAL[23:0]
0
These bits contain the peak value determined in the current channel.
24
IPPHASE[0]
0
When this bit is set to 1, Phase A current generated IPEAKVAL[23:0] value.
25
IPPHASE[1]
0
When this bit is set to 1, Phase B current generated IPEAKVAL[23:0] value.
26
IPPHASE[2]
0
When this bit is set to 1, Phase C current generated IPEAKVAL[23:0] value.
31:27
00000
These bits are always 0.
Table 36. VPEAK Register (Address 0xE501)
Bit Location
Bit Mnemonic
Default Value
Description
23:0
VPEAKVAL[23:0]
0
These bits contain the peak value determined in the voltage channel.
24
VPPHASE[0]
0
When this bit is set to 1, Phase A voltage generated VPEAKVAL[23:0] value.
25
VPPHASE[1]
0
When this bit is set to 1, Phase B voltage generated VPEAKVAL[23:0] value.
26
VPPHASE[2]
0
When this bit is set to 1, Phase C voltage generated VPEAKVAL[23:0] value.
31:27
00000
These bits are always 0.
Table 37. STATUS0 Register (Address 0xE502)
Bit
Location
Bit Mnemonic
Default Value
Description
0
AEHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the total active energy
registers (AWATTHR, BWATTHR, or CWATTHR) has changed.
1
FAEHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental active
energy registers, FWATTHR, BFWATTHR, or CFWATTHR, has changed. This bit is always 0
for ADE7854, ADE7858, and ADE7868.
2
REHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the total reactive energy
registers (AVARHR, BVARHR, or CVARHR) has changed. This bit is always 0 for ADE7854.
3
FREHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental reactive
energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed. This bit is always 0 for
ADE7854, ADE7858, and ADE7868.
4
VAEHF
0
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
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