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參數(shù)資料
| 型號： | ADE7878ACPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件頁數(shù)： | 28/96頁 |
| 文件大?。?/td> | 1096K |
| 代理商： | ADE7878ACPZ |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 34 of 96
PHASE B
PHASE C
PHASE A
ANGLE2
ANGLE0
ANGLE1
0
85
10
-0
32
Figure 46. Delays Between Phase Voltages (Currents)
The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit
unsigned registers with 1 LSB corresponding to 3.90625 μs
(256 kHz clock), which means a resolution of 0.0703° (360° ×
50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × 60 Hz/
256 kHz) for 60 Hz systems. The delays between phase voltages
or phase currents are used to characterize how balanced the
load is. The delays between phase voltages and currents are
used to compute the power factor on each phase as shown in
the following Equation 5:
cosφx = cos
×
kHz
256
360
LINE
f
ANGLEx
o
(5)
where fLINE = 50 Hz or 60 Hz.
Period Measurement
The ADE7854/ADE7858/ADE7868/ADE7878 provide the
period measurement of the line in the voltage channel. Bits[1:0]
(PERSEL[1:0]) in the MMODE register select the phase voltage
used for this measurement. The period register is a 16-bit
unsigned register and updates every line period. Because of the
LPF1 filter (see Figure 41), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period register
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the register enables the measurement of line frequencies
as low as 3.9 Hz (256 kHz/216). The period register is stable at
±1 LSB when the line is established and the measurement does
not change.
The following expressions can be used to compute the line
period and frequency using the period register:
[]
sec
3
E
256
1
+
=
0]
PERIOD[15:
T
L
(6)
]
Hz
[
1
3
E
256
+
=
0]
PERIOD[15:
f
L
(7)
Phase Voltage Sag Detection
The ADE7854/ADE7858/ADE7868/ADE7878 can be pro-
grammed to detect when the absolute value of any phase voltage
drops below a certain peak value for a number of half-line cycles.
The phase where this event takes place is identified in Bits[14:12]
(VSPHASE[x]) of the PHSTATUS register. This condition is
illustrated in Figure 47.
PHASE A VOLTAGE
BIT 16 (SAG) IN
STATUS1[31:0]
VSPHASE[0] =
PHSTATUS[12]
IRQ1 PIN
FULL SCALE
SAGLVL[23:0]
FULL SCALE
SAGLVL[23:0]
SAGCYC[7:0] = 0x4
PHASE B VOLTAGE
VSPHASE[1] =
PHSTATUS[13]
STATUS[16] AND
PHSTATUS[13]
SET TO 1
08
51
0-
03
3
STATUS1[16] AND
PHSTATUS[12]
CANCELLED BY A
WRITE TO
STATUS1[31:0]
WITH SAG BIT SET
SAGCYC[7:0] = 0x4
Figure 47. SAG Detection
Figure 47 shows Phase A voltage falling below a threshold that
is set in the SAG level register (SAGLVL) for four half-line cycles
(SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register is set
to 1 to indicate the condition, Bit VSPHASE[0] in the PHSTATUS
register is also set to 1 because the event happened on Phase A
Bit 16 (SAG) in the STATUS1 register. All Bits[14:12] (VSPHASE[2],
VSPHASE[1], and VSPHASE[0]) of the PHSTATUS register (not
just the VSPHASE[0] bit) are erased by writing the STATUS1
register with the SAG bit set to 1.
The SAGCYC register represents the number of half-line cycles
the phase voltage must remain below the level indicated in the
SAGLVL register to trigger a SAG condition; 0 is not a valid
number for SAGCYC. For example, when the SAG cycle
(SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (SAG) in
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